Ching-Che Chung

(Áé µ× ­õ)

Professor and Chairman

Department of Computer Science and Information Engineering (CSIE)

National Chung Cheng University

EA406, CSIE Building,

No.168, Sec. 1, University Rd., Minhsiung, Chiayi 621301, Taiwan (R.O.C.)

TEL: +886-5-272-9395

FAX: +886-5-272-0859

E-mail: wildwolf_AT_cs.ccu.edu.tw

 

621301¹Å¸q¿¤¥Á¶¯¶m¤j¾Ç¸ô¤@¬q168¸¹ ¤¤¥¿¤j¾Ç¸ê¤uÀ] 406 «Ç (¤¤¥¿¤j¾Ç¦a¹Ï)

¿ì¤½«Çª½¼·¹q¸Ü: (05) 272-9395 (©Î¼·¤¤¥¿Á`¾÷ (05) 272-0411 Âà¤À¾÷: 33129)

¶Ç¯u¡G(05) 272-0859

ºô­¶§ó·s¤é´Á¡G 2024/01/24

ocam: https://www.cs.ccu.edu.tw/~wildwolf/ocam.zip

pointer: https://www.cs.ccu.edu.tw/~wildwolf/pointer.zip

¤¤¥¿¤j¾ÇªÅ®ð«~½è§Y®É¸ê°T:

CCU Air Quality

¾Ç¸g¾ú (Professional Background):

[2017.08 ¡V Present ] °ê¥ß¤¤¥¿¤j¾Ç ¸ê°T¤uµ{¾Ç¨t ±Ð±Â

[2022.08 ¡V Present ] »OÆW¿nÅé¹q¸ô³]­p¾Ç·|(TICD) ²z¨Æ

[2012.08 ¡V 2017.07] °ê¥ß¤¤¥¿¤j¾Ç ¸ê°T¤uµ{¾Ç¨t °Æ±Ð±Â

[2008.08 ¡V 2012.07] °ê¥ß¤¤¥¿¤j¾Ç ¸ê°T¤uµ{¾Ç¨t §U²z±Ð±Â

[2008.01 ¡V 2008.07] °ê¥ß¥æ³q¤j¾Ç ´¹¤ù¨t²Î¬ã¨s¤¤¤ß ³Õ¤h«á¬ã¨s

[2004.02 ¡V 2009.11] °]¹Îªk¤H¹©¤Ñ¬ì§Þ±Ð¨|°òª÷·| ¸³¨Æ

[2004.01 ¡V 2008.01] °ê¥ß¥æ³q¤j¾Ç ¹q¤l¬ã¨s©Ò¨t²Î²Õ ³Õ¤h«á¬ã¨s

[1998.09 ¡V 2003.09] °ê¥ß¥æ³q¤j¾Ç ¹q¤l¬ã¨s©Ò¨t²Î²Õ ³Õ¤h

ºaÅA (Awards):

1.      Most-Read JSSC Articles for 2003 (Recognized by: IEEE, posted Mar 8. 2004.)

2.      2004, ¡§§»ùÖÀsÄ˽פå¼ú,¡¨ Àuµ¥

3.      2006, ¡§Low Power Design Contest Award,¡¨ at International Symposium on Low Power Electronics and Design (ISLPED)

4.      2011, ¡§Criti-Core ¤§·Å«×·Pª¾»P¹q·½ºÞ²z¹q¸ô³]­p¡¨¡A°ê¬ì·|¾ã¦X«¬­pµe¡uÁZÀu­pµe¼ú¡v

5.      2013, ¡§°ê¥ß¤¤¥¿¤j¾Ç¤u¾Ç°|101¾Ç¦~«×«C¦~¾ÇªÌ¼ú¡¨

6.      2015, ¡§°ê¥ß¤¤¥¿¤j¾Ç¤u¾Ç°|103¾Ç¦~«×«C¦~¾ÇªÌ¼ú¡¨

7.      2015, ¡§¡u104 ¾Ç¦~«×¼úÀyÁÚ¦V³»¦y¤j¾Ç¯S®íÀu¨q¬ã¨s¤H¤~º[°õ¦æ«e¤»s³y¨t²Î³»¦y¬ã¨s¤¤¤ß­pµeÁZÀu±Ð®v¼u©ÊÁ~¸ê®×¡v¼úÀyª÷¡¨

8.      2016, ¡§¡u105 ¾Ç¦~«×¼úÀyÁÚ¦V³»¦y¤j¾Ç¯S®íÀu¨q¬ã¨s¤H¤~º[°õ¦æ«e¤»s³y¨t²Î³»¦y¬ã¨s¤¤¤ß­pµeÁZÀu±Ð®v¼u©ÊÁ~¸ê®×¡v¼úÀyª÷¡¨

9.      2017, ¡§Best Paper Award, second place,¡¨ at IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)

10.  2018, ¡§°ê¥ß¤¤¥¿¤j¾Ç¤u¾Ç°|105¾Ç¦~«×Àu¨}±Ð¾Ç¼ú¡¨

11.  2018, ¡§°ê¥ß¤¤¥¿¤j¾Ç107¦~«×±Ð®v¬ã¨sµo®i¼úÀy¡¨

12.  2019, ¡§°ê¥ß¤¤¥¿¤j¾Ç107¾Ç¦~«×¥þ®Õ±Ð®vÀu¨}±Ð¾Ç¼ú¡¨

13.  2019, ¡§°ê¥ß¤¤¥¿¤j¾Ç108¾Ç¦~«×¼u©ÊÁ~¸ê¼úÀy¡¨

14.  2020, ¡§°ê¥ß¤¤¥¿¤j¾Ç«e¤»s³y¨t²Î³»¦y¬ã¨s¤¤¤ß 109 ¾Ç¦~«×¡u±Ð®v¼úÀy¡v¡¨

15.  2021, ¡§IEET ¤¤µØ¤uµ{±Ð¨|¨ó·|2021¦~«×±Ð¾Ç³Ç¥X¼ú(IEET Distinguished Teaching Award)¡¨

16.  2021, ¡§ViewSonic ³Ð·s±Ð®v¼ú ¡V ½Æ¦X±Ð¾Ç¥Ü½dÄvÁÉÀuµ¥¼ú¡¨

17.  2022,¡§°ê¥ß¤¤¥¿¤j¾Ç110¾Ç¦~«×¥þ®Õ±Ð®vÀu¨}±Ð¾Ç¼ú¡¨

18.  2023, ¡§°ê¥ß¤¤¥¿¤j¾Ç«e¤»s³y¨t²Î³»¦y¬ã¨s¤¤¤ß 111 ¾Ç¦~«×¡u±Ð®v¼úÀy¡v¡¨

¬ã¨s¤è¦V (Research Topics):

1.      Wireless and Wireline Communication Systems

2.      Low-Power and System-on-a-Chip (SOC) Design Technology

3.      Mixed-Signal IC Design and Sensor Circuits Design

4.      Deep Learning Hardware Design

5.      All-digital Phase-Locked Loop/Delay-Locked Loop and Its Applications

ª¿·P´ú¾¹»P¨t²Î¹êÅç«Ç (Silicon Sensor and System Lab, S3Lab):

 

¹êÅç«Ç¦¨­û

 

¸ê¤u¨t¶}³]½Òµ{ (Open Courses):

1.      ¤uµ{¼Æ¾Ç (Engineering Mathematics)

¶}½Ò¤é´Á: 2008/09/17, 2009/09/16, 2010/09/15, 2011/9/14, 2016/09/14,

2017/09/20, 2018/09/12, 2019/09/11

2.      ¼Æ¦ì¿nÅé¹q¸ô³]­p (Design of Digital Integrated Circuits and Systems)

¶}½Ò¤é´Á: 2009/02/16, 2010/02/23, 2011/02/22, 2012/02/22, 2013/02/20,

2014/02/19, 2015/02/25, 2016/02/24, 2017/02/22, 2018/03/07, 2019/02/20,

2020/03/04, 2021/02/24, 2022/02/16, 2023/02/15, 2024/02/21

3.      °ªµ¥¼Æ¦ì¿nÅé¹q¸ô³]­p (Advanced Digital Integrated Circuits Design)

¶}½Ò¤é´Á¡G2009/09/15, 2010/09/14, 2011/09/13, 2012/09/18, 2013/09/17,

2014/09/17, 2015/09/15, 2016/09/13, 2017/09/19, 2018/09/11, 2019/09/10, 2020/09/08, 2021/09/14, 2022/09/06, 2023/09/05

4.      ¶W¤j«¬¿nÅé¹q¸ô³]­p·§½× (Basic VLSI Systems Design)

¶}½Ò¤é´Á¡G2010/02/22, 2011/02/21, 2012/02/24, 2013/02/22, 2014/02/21, 2015/03/06, 2016/02/26 (¥þ­^¤å±Â½Ò), 2017/02/24 (¥þ­^¤å±Â½Ò), 2018/03/02 (¥þ­^¤å±Â½Ò), 2019/02/22 (¥þ­^¤å±Â½Ò), 2020/03/06 (¥þ­^¤å±Â½Ò), 2021/02/26 (¥þ­^¤å±Â½Ò), 2022/02/18 (¥þ­^¤å±Â½Ò), 2023/02/17 (¥þ­^¤å±Â½Ò), 2024/02/23 (¥þ­^¤å±Â½Ò)

5.      ¼Æ¦ì¹q¤l¾Ç (Electronic Circuits and Electronics)

¶}½Ò¤é´Á¡G2012/09/17, 2013/09/16, 2014/09/18, 2015/09/16, 2020/09/09, 2021/09/15 (¥þ­^¤å±Â½Ò), 2022/09/07 (¥þ­^¤å±Â½Ò), 2023/09/06 (¥þ­^¤å±Â½Ò)

¬ã¨s­pµe(Projects):

¶µ¥Ø

­pµe¦WºÙ

¸g¶O¨Ó·½

°õ¦æ´Á¶¡

1

¿nÅé¹q¸ô³]­p¬ÛÃö½Òµ{ªº¹CÀ¸¤Æ±Ð¾ÇÀ³¥Î©ó»·¶Z±Ð¾Ç½Òµ{ (±Ð¾Ç¹ê½î¬ã¨s­pµe)

±Ð¨|³¡

PEE1121357

2023/08/01 ~ 2024/07/31

2

111 ¦~«×´¹¤ù«e¤§Þ³N¼Ò²Õ±Ð§÷µo®i­pµe

«e¤¹Bºâ¡GÃä½t¹Bºâ¤H¤u´¼¼z´¹¤ù§C¥\²v³Ì¨Î¤Æ

±Ð¨|³¡

2022/10/01 ~ 2023/09/30

3

±j¤Æª«Ápºô²×ºÝ´¹¤ù¤u§@Àô¹ÒºÊ±±»P«Ø¥ßµwÅé¦w¥þ¨t²Î¤§¬ã¨s(II)  (¤@¯ë«¬¬ã¨s­pµe)

¬ì§Þ³¡

MOST 111 - 2221 - E -194 - 049 -

2022/08/01 ~ 2023/07/31

4

±j¤Æª«Ápºô²×ºÝ´¹¤ù¤u§@Àô¹ÒºÊ±±»P«Ø¥ßµwÅé¦w¥þ¨t²Î¤§¬ã¨s  (¤@¯ë«¬¬ã¨s­pµe)

¬ì§Þ³¡

MOST 110 - 2221 - E -194 - 045 -

2021/08/01 ~ 2022/07/31

5

¶}µo²`«×¾Ç²ßºô¸ôµwÅé¥[³t¾¹À³¥Î©ó¤u¨ã¾÷¬G»Ù¶EÂ_¤Î¹w¨¾©ÊºûÅ@(I)  (¤@¯ë«¬¬ã¨s­pµe)

¬ì§Þ³¡

MOST 108 - 2221 - E -194 - 051 -

2019/08/01 ~ 2020/07/31

6

¾A¥Î©óÁn­µ±¡¹Ò¤ÀªR¤§²`¼hÃþ¯«¸gºô¸ôµwÅé¥[³t¾¹³]­p¤Î¨äÀ³¥Î¤§¸`¯à¥­¥x(I) (¤@¯ë«¬¬ã¨s­pµe)

¬ì§Þ³¡

MOST 107 - 2221 - E -194 - 031 -

2018/08/01 ~ 2019/07/31

7

Án­µ±¡¹Ò¤ÀªR¡BÀ³¥Î¤Î¨ä¸`¯à¹q¸ô¨t²Î³]­p--¤l­pµe¥|¡G¾A¥Î©óÁn­µ±¡¹Ò¤ÀªR»PÀ³¥Î¤§¸`¯à¥­¥x¤Î¨ä²`¼hÃþ¯«¸gºô¸ôµwÅé¥[³t¾¹³]­p   (¤@¯ë«¬¬ã¨s­pµe)

¬ì§Þ³¡

MOST 106 - 2221 - E -194 - 059 -

2017/08/01 ~ 2018/07/31

8

´¼¼z¹q¤l¾ã¦X©Ê¤H¤~°ö¨|­pµe ¡V °ª¶¥À³¥Î³B²z¾¹(AP)¬ÛÃö¼Ò²Õ½Òµ{µo®i­pµe - ¡u´¹¤ù®É¯ß³d¥ô¶g´Á®Õ¥¿¹q¸ô³]­p¡v¼Ò²Õ½Òµ{­pµe(²Ä¤T¦~)

±Ð¨|³¡

2015/03/01

~

2016/04/30

9

1Mbps ¡V 40Mbps ¤HÅé³q¹D¶Ç¦¬¾¹³]­p (Àu¨q¦~»´¾ÇªÌ¬ã¨s­pµe)

¬ì§Þ³¡

MOST 103 - 2221 - E -194 - 063 -MY3

2014/08/01

~

2017/07/31

10

´¼¼z¹q¤l¾ã¦X©Ê¤H¤~°ö¨|­pµe ¡V °ª¶¥À³¥Î³B²z¾¹(AP)¬ÛÃö¼Ò²Õ½Òµ{µo®i­pµe - ¡u§C¥\²v´¹¤ù°Ñ¦Ò®É¯ß¹q¸ô³]­p¡v¼Ò²Õ½Òµ{­pµe (²Ä¤G¦~)

±Ð¨|³¡

2014/03/01

~

2015/02/28

11

¥i¶W¼e½ÕÀ£¤§´¼¼zµøı³B²z´¹¤ù¨t²Î¥­¥x ¡V ¤l­pµe¥|¡G°w¹ï UDVS SoC ¶}µo¤§¥þ¼Æ¦ì®É¯ß²£¥Í¾¹»P´¹¤ù¶×¬y±Æ³]­p (¤@¯ë«¬¬ã¨s­pµe)

°ê¬ì·|

NSC 102 - 2221 - E -194 - 063 -MY3

2013/08/01 ~ 2016/07/31

12

´¼¼z¹q¤l¾ã¦X©Ê¤H¤~°ö¨|­pµe ¡V °ª¶¥À³¥Î³B²z¾¹(AP)¬ÛÃö¼Ò²Õ½Òµ{µo®i­pµe - ¡u§C¥\²v®É¯ß²£¥Í¾¹¡v¼Ò²Õ½Òµ{­pµe (²Ä¤@¦~)

±Ð¨|³¡

2012/12/01

~

2014/02/28

13

°w¹ï A-UDVS iVP SoC ¶}µo¤§§ÜÅܲ§¥þ¼Æ¦ì®É¯ß²£¥Í¾¹»P´¹¤ù¶×¬y±Æ³]­p (¤@¯ë«¬¬ã¨s­pµe)

°ê¬ì·|

NSC101 - 2221 - E - 194 - 063

2012/08/01 ~ 2013/07/31

14

¾A¥Î©ó§Ö°{°O¾ÐÅé¨t²Î¤§¿ù»~§ó¥¿½s¸Ñ½X¤Î¨äµwÅé¬[ºc

«Ø¿³¹q¤l(LiteOn)

2012/06/01

~

2014/06/30

15

¥Î©óDRAM±±¨î¤§¼Æ¦ì©µ¿ðÂê©w°j¸ô¬ã¨s

®ü«ä¥b¾ÉÅé

2011/12/01

~

2012/11/30

16

´¼¼z¹q¤l¾ã¦X©Ê¤H¤~°ö¨|­pµe - ±Ð¨|³¡ÅU°Ý«Ç

ÂåÀø¹q¤l»â°ì -¥ÍÂå¼v¹³³B²z¨t²Î

±Ð¨|³¡

2011/09/01

~

2014/01/01

17

§C¥\²vÀx¦s¨t²Î»P°ª³t¶Ç¿é¬É­±¹q¸ô³]­p for iF2 Diary) (¤@¯ë«¬¬ã¨s­pµe)

°ê¬ì·|

NSC100 - 2221 - E - 194 - 051

2011/08/01 ~ 2012/07/31

18

«e¤´¹¤ù¨t²Î³]­p¤H¤~°ö¨|¥ý¾É«¬­pµe ¡V ½Òµ{µo®i­pµe ¡V ±Ð§÷µo®i ¡V ¨t²Î´¹¤ùÅçÃÒ¥­¥x»P¹ê§@¾ã¦X½Òµ{

±Ð¨|³¡

2010/03/01 ~ 2010/12/31

19

Criti-core: ¶W¶V¦h®Ö¤ß¤§°ª¥i¾a«×´¹¤ù¨t²Î¥­¥x§Þ³N¶}µo ¡V ¤l­pµe¥|¡GCriti-Core ¤§·Å«×·Pª¾»P¹q·½ºÞ²z¹q¸ô³]­p (°ê®a«¬¬ì§Þ­pµe)

°ê¬ì·|

NSC98 - 2220 - E - 194 - 013

NSC 99 - 2220 - E - 194 - 011

2009/08/01 ~ 2011/07/31

20

«e¤´¹¤ù¨t²Î³]­p¾Çµ{­pµe--´O¤J¦¡¨t²Î³nÅé¾Çµ{(ESW)

±Ð¨|³¡

2009/03/01 ~ 2011/01/31

21

§Ö³t¬Û¦ìÂê©w°ªÀW²v­¿¼Æ¥þ¼Æ¦ìÂê¬Û°j¸ô³]­p»PÀ³¥Î¤§¬ã¨s (·s¶i¤H­û¬ã¨s­pµe)

°ê¬ì·|

NSC 97 - 2218 - E - 194 - 009 - MY2

2008/11/01 ~ 2010/07/31

22

¨Ï¥Î¥u»Ýª÷Äݼh«K¥i­«·sµ{¦¡¤Æªº¼Ð·Ç¤¸¥ó®w¶}µo¥þ¼Æ¦ì¦h¬Û¦ì®É¯ß²£¥Í¾¹¤Î¥þ¼Æ¦ìÂê¬Û°j¸ô¥Î©ó0.13um CMOS»sµ{ªºSoC²£«~¶}µo(Develop All-Digital Multi-Phase Clock Generator and All-Digital Phase-Locked Loop on Metal Programmable Cell Array (MPCA) for SoC products on 0.13um CMOS Process)

´¼­ì¬ì§Þ(Faraday)

2005/01/01 ~ 2005/12/31

¤wµoªíµÛ§@ªº³Q¤Þ¥Î±¡§Î(My Citations)

Google Scholar (Author: Ching-Che Chung)

Scopus Data (Scopus ID: 57762571600)

¤wµoªíµÛ§@ (´Á¥Z Journal Papers):

// Impact Factor (IF): 2022 JCR Science Edition (https://www.isiknowledge.com/JCR)

// H-index: 19 (by Google Scholar) (https://en.wikipedia.org/wiki/H-index)

// SCI Citation Count (https://www.isiknowledge.com)

// Google Citation Count (https://scholar.google.com.tw/)

1.      Yu-Pei Liang, Yao-Shun Hsu (¾Ç¥Í), and Ching-Che Chung*, ¡§A low-power hierarchical CNN hardware accelerator for bearing fault diagnosis,¡¨ IEEE Transactions on Instrumentation and Measurement, vol. 73, Art no. 3508511, Jan. 2024. [pdf] [SCI, EI, IF=5.6, Rank=9/63 (14.2%) in Instruments and Instrumentation, Rank=56/275 (20.3%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST111-2221-E-194-049)

2.      Yu-Pei Liang, Ming-You Hung (¾Ç¥Í), and Ching-Che Chung*, ¡§A multiplier-free convolution neural network hardware accelerator for real-time bearing condition detection of CNC machinery,¡¨ Sensors, vol. 23, no. 23, Art no. 9437, Nov. 2023. [pdf] [SCI, EI, IF=3.9, Rank=100/275 (36.3%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST111-2221-E-194-049)

3.      Ching-Che Chung*, Yu-Pei Liang, and Hong-Jin Jiang (¾Ç¥Í), ¡§CNN hardware accelerator for real-time bearing fault diagnosis,¡¨ Sensors, vol. 23, no. 13, Art no. 5897, Jun. 2023. [pdf] [SCI, EI, IF=3.9, Rank=100/275 (36.3%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST111-2221-E-194-049)

4.      Tsung-Hsien Liu*, Ting-Xu Jiang (¾Ç¥Í), Ching-Che Chung, and Yuan-Sun Chu, ¡§A maximum logarithmic maximum a posteriori probability based soft-input soft-output detector for the coded spatial modulation systems,¡¨ IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 69, no. 9, pp. 3816-3828, Sep. 2022. [pdf] [SCI, EI, IF=5.1, Rank=68/275 (24.7%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST109-2221-E-194-032-MY2)

5.      Ching-Che Chung*, Duo Sheng, and Ming-Hsuan Li (¾Ç¥Í), ¡§Design of a Human Body Channel Communication Transceiver Using Convolutional Codes,¡¨ Microelectronics Journal, vol. 100, Art no. 104783, Jun. 2020. [pdf] [SCI, EI, IF=1.405, Rank=192/266 (72.2%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST108-2221-E-194-051)

6.      Ching-Che Chung*, Duo Sheng, Ming-Chieh Li (¾Ç¥Í), and Yi-Che Tsai (¾Ç¥Í), ¡§A fast phase tracking reference-less all-digital CDR circuit for human body channel communication,¡¨ Microelectronics Journal, vol. 84, pp. 87-95, Feb. 2019. [pdf] [SCI, EI, IF=1.405, Rank=192/266 (72.2%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST107-2221-E-194-031)

7.      Ching-Che Chung* and Chi-Yu Hou (¾Ç¥Í), ¡§An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications,¡¨ Microelectronics Journal, vol. 70, pp. 63-71, Dec. 2017. [pdf] [SCI, EI, IF=1.322, Rank=175/260 (67.3%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST103-2221-E- 194-063-MY3)

8.      Ching-Che Chung* and Chien-Ying Yu (¾Ç¥Í), ¡§An area-efficient and wide-range digital DLL for per-pin deskew applications,¡¨ Turkish Journal of Electrical Engineering and Computer Sciences, vol. 25, no. 3, pp. 2185-2194, May 2017. [pdf] [SCI, EI, IF=0.580, Rank=231/260 (88.8%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST103-2221-E- 194-063-MY3)

9.      Ching-Che Chung* and Jhih-Wei Li (¾Ç¥Í), ¡§A cell-based 5-MHz on-chip clock generator,¡¨ Turkish Journal of Electrical Engineering and Computer Sciences, vol. 25, no. 2, pp. 1472-1482, Apr. 2017. [pdf] [SCI, EI, IF=0.580, Rank=231/260 (88.8%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC102-2221-E-194- 063-MY3)

10.  Ching-Che Chung* and Chi-Kuang Lo (¾Ç¥Í), ¡§A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology, ¡§ IEICE Electronics Express (ELEX), vol. 13, no. 17, 20160749, Aug. 2016. [pdf] [SCI, EI, IF=0.456, Rank=245/262 (93.5%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST103-2221-E- 194-063-MY3)

11.  Ching-Che Chung*, Wei-Siang Su(¾Ç¥Í), and Chi-Kuang Lo(¾Ç¥Í), ¡§A 0.52V/1.0V fast lock-in ADPLL for supporting dynamic voltage and frequency scaling,¡¨ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1, pp. 408-412, Jan. 2016. [pdf] [SCI, EI, IF=1.698, Rank=21/52 (40.4%) in Computer Science, Hardware & Architecture, Rank=127/262 (48.5%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC102-2221-E-194-063-MY3)

12.  Ching-Che Chung*, Duo Sheng, and Chang-Jun Li(¾Ç¥Í), ¡§A wide-range low-cost all-digital duty-cycle corrector,¡¨ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2487-2496, Nov. 2015. [pdf] [SCI, EI, IF=1.245, Rank=19/51 (37.3%) in Computer Science, Hardware & Architecture, Rank=132/257 (51.4%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC102-2221-E-194-063-MY3)

13.  Ching-Che Chung*, Duo Sheng, and Wei-Da Ho(¾Ç¥Í), ¡§A low-cost low-power all-digital spread-spectrum clock generator,¡¨ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 983-987, May 2015. [pdf] [SCI, EI, IF=1.245, Rank=19/51 (37.3%) in Computer Science, Hardware & Architecture, Rank=132/257 (51.4%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC102-2221-E-194-063-MY3)

14.  Ching-Che Chung* and Hao-Hsiang Hsu(¾Ç¥Í), ¡§Partial parity cache and data cache management method to improve the performance of an SSD-based RAID,¡¨ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 7, pp. 1470-1480, Jul. 2014. [pdf] [SCI, EI, IF=1.356, Rank=16/50 (32.0%) in Computer Science, Hardware & Architecture, Rank=111/249 (44.6%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC100-2221-E-194-051)

15.  Ching-Che Chung*, Duo Sheng, and Sung-En Shen(¾Ç¥Í), ¡§High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology,¡¨ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1096-1105, May 2014. [pdf] [SCI, EI, IF=1.356, Rank=16/50 (32.0%) in Computer Science, Hardware & Architecture, Rank=111/249 (44.6%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC101-2221-E-194-063)

16.  Duo Sheng*, Ching-Che Chung, Hsiu-Fan Lai(¾Ç¥Í), and Shu-Syun Jhao(¾Ç¥Í), ¡§High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications, ¡§ IEICE Electronics Express (ELEX) , vol. 11, no. 3, 20131011, Jan. 2014. [pdf] [SCI, EI, IF=0.391, Rank=211/248 (85.1%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC101-2221-E-030-025)

17.  Ching-Che Chung*, Duo Sheng, and Wei-Da Ho(¾Ç¥Í), ¡§A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS, ¡§ IEICE Electronics Express (ELEX), vol. 10, no. 6, 20130090, Mar. 2013. [pdf] [SCI, EI, IF=0.391, Rank=211/248 (85.1%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC101-2221-E-194-063)

18.  Ching-Che Chung*, Duo Sheng, and Ning-Mi Hsueh(¾Ç¥Í), ¡§A high-performance wear-leveling algorithm for flash memory system, ¡§ IEICE Electronics Express (ELEX), vol. 9, no. 24, pp. 1874-1880, Dec. 2012. [pdf] [SCI, EI, IF=0.268, Rank=223/243 (91.7%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 1] (NSC100-2221-E-194-051)

19.  Wei-Hao Sung(¾Ç¥Í), Ming-Che Lee(¾Ç¥Í), Ching-Che Chung, and Chen-Yi Lee*, ¡§An ultra-low voltage implicit multiplexed differential flip-flop with enhanced noise immunity,¡¨  Electronics Letters, vol. 48, no. 23, pp. 1452-1454, Nov. 2012. [pdf] [SCI, EI, IF=1.038, Rank=128/243 (52.6%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC100-2220-E-009-016)

20.  Chien-Ying Yu(¾Ç¥Í), Ching-Che Chung, Chia-Jung Yu(¾Ç¥Í), and Chen-Yi Lee*, ¡§A low-power DCO using interlaced hysteresis delay cells, ¡§ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 10, pp. 673-677, Oct. 2012. [pdf] [SCI, EI, IF=1.327, Rank=96/243 (39.5%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC100-2220-E-009-016)

21.  Ching-Che Chung*, Duo Sheng, Chia-Lin Chang(¾Ç¥Í), Wei-Da Ho(¾Ç¥Í), Yang-Di Lin(¾Ç¥Í), and Fang-Nien Lu(¾Ç¥Í), ¡§An all-digital large-N audio frequency synthesizer for HDMI applications, ¡§ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 7, pp. 424-428, Jul. 2012. [pdf] [SCI, EI, IF=1.327, Rank=96/243 (39.5%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC100-2221-E-194-051)

22.  Duo Sheng*, Ching-Che Chung, Jhih-Ci Lan(¾Ç¥Í), and Hsiou-Fan Lai(¾Ç¥Í), ¡§Monotonic and low-power digitally controlled oscillator with portability for SoC applications,¡¨  Electronics Letters, vol. 48, no. 6, pp. 321-323, Mar. 2012. [pdf] [SCI, EI, IF=1.038, Rank=128/243 (52.6%) in Engineering, Electrical Electronics, SCI Cited: 1, Google Cited: 0] (NSC100-2221-E-030-012)

23.  Ching-Che Chung* and Chiun-Yao Ko(¾Ç¥Í), ¡§A fast phase tracking ADPLL for video pixel clock generation in 65 nm CMOS technology, ¡§ IEEE Journal of Solid-State Circuits, vol. 46, no. 10, pp. 2300-2311, Oct. 2011. [pdf] [SCI, EI, IF=3.226, Rank=15/245 (6.1%) in Engineering, Electrical Electronics, SCI Cited: 3, Google Cited: 16] (NSC97-2218-E-194-009-MY2)

24.  Ching-Che Chung*, Duo Sheng, and Sung-En Shen(¾Ç¥Í), ¡§A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65 nm CMOS technology, ¡§ IEICE Electronics Express (ELEX) , vol. 8, no. 15, pp. 1245-1251, Aug. 2011. [pdf] [SCI, EI, IF=0.461, Rank=195/245 (79.6%) in Engineering, Electrical Electronics, SCI Cited: 2, Google Cited: 1] (NSC99-2220-E-194-011)

25.  Ching-Che Chung*, Jui-Yuan Yu(¾Ç¥Í), Shiou-Ru Jang(¾Ç¥Í), and Chen-Yi Lee, ¡§A 90 nm all-digital smart temperature sensor with wireless body area network baseband transceiver for biotelemetry applications,¡¨ Journal of Signal Processing Systems for Signal Image and Video Technology, vol. 46, no. 2, pp. 241-248, Aug. 2011. [pdf] [SCI, EI, IF=0.672, Rank=165/245 (67.3%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC99-2220-E-194-011)

26.  Duo Sheng, Ching-Che Chung, and Chen-Yi Lee*, ¡§A low-power and portable spread spectrum clock generator for SoC applications,¡¨ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 6, pp. 1113-1117, Jun. 2011. [pdf] [SCI, EI, IF=1.219, Rank=15/50 (30.0%) in Computer Science, Hardware & Architecture, Rank=105/245 (42.8%) in Engineering, Electrical Electronics, SCI Cited: 4, Google Cited: 7] (NSC96-2221-E-009-181)

27.  Ching-Che Chung*, Duo Sheng, and Chia-Lin Chang(¾Ç¥Í), ¡§A 600 kHz to 1.2 GHz all-digital delay-locked loop in 65 nm CMOS technology,¡¨ IEICE Electronics Express (ELEX), vol. 8, no. 7, pp. 518-524, Apr. 2011. [pdf] [SCI, EI, IF=0.461, Rank=195/245 (79.6%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC97-2218-E-194-009-MY2)

28.  Ching-Che Chung*, Chiun-Yao Ko(¾Ç¥Í), and Sung-En Shen(¾Ç¥Í), ¡§Built-in self-calibration circuit for monotonic digitally controlled oscillator design in 65-nm CMOS technology, ¡§ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 3, pp. 149-153, Mar. 2011. [pdf]. [SCI, EI, IF=1.410, Rank=88/245 (35.9%) in Engineering, Electrical Electronics, SCI Cited: 3, Google Cited: 4] (NSC97-2218-E-194-009-MY2)

29.  Ching-Che Chung* and Cheng-Ruei Yang(¾Ç¥Í), ¡§An autocalibrated all-digital temperature sensor for on-chip thermal monitoring, ¡§ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 2, pp. 105-109, Feb. 2011. [pdf] [SCI, EI, IF=1.410, Rank=88/245 (35.9%) in Engineering, Electrical Electronics, SCI Cited: 7, Google Cited: 28] (NSC99-2220-E-194-011)

30.  Duo Sheng(¾Ç¥Í), Ching-Che Chung, and Chen-Yi Lee*, ¡§Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications,¡¨ IEICE Electronics Express (ELEX), vol. 7, no. 9, pp. 634-639, May 2010. [pdf] [SCI, EI, IF=0.427, Rank=195/247 (78.9%) in Engineering, Electrical Electronics, SCI Cited: 2, Google Cited: 4] (NSC96-2221-E-009-181)

31.  Duo Sheng(¾Ç¥Í), Ching-Che Chung, and Chen-Yi Lee*, ¡§Wide duty cycle range synchronous mirror delay designs,¡¨ Electronics Letters, vol. 46, no. 5, pp. 338-340, Mar. 2010. [pdf] [SCI, EI, IF=1.004, Rank=124/247 (50.2%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC96-2221-E-009-181)

32.  Jui-Yuan Yu(¾Ç¥Í), Ching-Che Chung, and Chen-Yi Lee*, ¡§A symbol-rate timing synchronization method for low power wireless OFDM systems,¡¨ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 9, pp. 922-926, Sep. 2008. [pdf] [SCI, EI, IF=1.436, Rank=78/229 (34.1%) in Engineering, Electrical Electronics, SCI Cited: 3, Google Cited: 7] (MOEA 95-EC-17-A-03-S1-0005)

33.  Duo Sheng(¾Ç¥Í), Ching-Che Chung, and Chen-Yi Lee*, ¡§An ultra-low-power and portable digitally controlled oscillator for SoC applications,¡¨ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 11, pp. 954-958, Nov. 2007. [pdf] [SCI, EI, IF=1.104, Rank=76/227 (33.5%) in Engineering, Electrical Electronics, SCI Cited: 18, Google Cited: 48] (NSC95-2220-E-009-291)

34.  Pao-Lung Chen(¾Ç¥Í), Ching-Che Chung, Jyh-Neng Yang, and Chen-Yi Lee*, ¡§A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications,¡¨ IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1275-1285, Jun. 2006. [pdf] [SCI, EI, IF=2.002, Rank=25/206 (12.1%) in Engineering, Electrical Electronics, SCI Cited: 24, Google Cited: 44] (NSC93-2220-E-009-033)

35.  Pao-Lung Chen(¾Ç¥Í), Ching-Che Chung, and Chen-Yi Lee*, ¡§A portable digitally controlled oscillator using novel varactors,¡¨ IEEE Transaction on Circuits and System II: Analog and Digital Signal Processing, vol. 52, no. 5, pp. 233-237, May 2005. [pdf] [SCI, EI, IF=0.661, Rank=110/208 (52.9%) in Engineering, Electrical Electronics, SCI Cited: 32, Google Cited: 75] (NSC93-2220-E-009-033)

36.  Pao-Lung Chen(¾Ç¥Í), Ching-Che Chung, and Chen-Yi Lee*, ¡§A novel digitally-controlled varactor for portable delay cell design,¡¨ IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E87-A, no .12, pp. 3324-3326, Dec. 2004. [pdf] [SCI, EI, IF=0.318, Rank=154/209 (73.7%) in Engineering, Electrical Electronics, SCI Cited: 4, Google Cited: 2] (NSC92-2220-E-009-019)

37.  Ching-Che Chung and Chen-Yi Lee*, ¡§A new DLL-based approach for all-digital multiphase clock generation,¡¨ IEEE Journal of Solid-State Circuits, vol. 39, no. 3, pp. 469-475, Mar. 2004. [pdf] [SCI, EI, IF=1.756, Rank=29/209 (13.9%) in Engineering, Electrical Electronics, SCI Cited: 32, Google Cited: 61] (NSC90-2215-E-009-105)

38.  Ching-Che Chung and Chen-Yi Lee*, ¡§An all-digital phase-locked loop for high-speed clock generation,¡¨ IEEE Journal of Solid-State Circuits, vol.38, no. 2, pp. 347-351, Feb. 2003. [pdf] [SCI, EI, IF=2.035, Rank=22/205 (10.7%) in Engineering, Electrical Electronics, SCI Cited: 73, Google Cited: 160] (NSC90-2215-E-009-105)

¤wµoªíµÛ§@ (­«­n°ê»Ú·|ij Top Conferences):

1.      Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao and Chen-Yi Lee, ¡§A sub-mW multi-tone CDMA baseband transceiver chipset for wireless body area network applications, ¡§ in Digest of Technical Papers, IEEE Solid-State Circuits Conference (ISSCC), Feb. 2007, pp. 364-365. [pdf] [EI, Google Cited: 8] (MOEA 95-EC-17-A-03-S1-0005)

2.      Tsu-Ming Liu, Ching-Che Chung, Ting-An Lin, Sheng-Zen Wang, and Chen-Yi Lee, ¡§Design of a 125mW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications, ¡§ in Proceedings of 43rd ACM/IEEE Design Automation Conference (DAC), Jul. 2006, pp. 288-289. [pdf] [EI, Google Cited: 7] (NSC94-2215-E-009-046)

3.       Summary: Not available.Jui-Yuan Yu, Ching-Che Chung, Hsuan-Yu Liu, Yu-Wei Lin, Wan-Chun Liao, Terng-Yin Hsu, and Chen-Yi Lee, ¡§A 31.2mW UWB baseband transceiver with all-digital I/Q-mismatch calibration and dynamic sampling, ¡§ in Digest of Technical Papers, Symposium on VLSI Circuits, Jun. 2006, pp. 236-237. [pdf] [EI, Google Cited: 10] (MOEA 95-EC-17-A-03-S1-0005)

4.      Hsuan-Yu Liu, Chien-Ching Lin, Yu-Wei Lin, Ching-Che Chung, Kai-Li Lin, Wei-Che Chang, Lin-Hung Chen, Hsie-Chia Chang, and Chen-Yi Lee, ¡§A 480Mb/s LDPC-COFDM-based UWB baseband transceiver, ¡§ in Digest of Technical Papers, IEEE Solid-State Circuits Conference (ISSCC), Feb. 2005, pp.444-446. [pdf] [EI, Google Cited: 37] (MOEA 95-EC-17-A-03-S1-0005)

5.      Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Ching Lin, Ching-Che Chung, Terng-Yi Hsu, and Chen-Yi Lee, ¡§A COFDM baseband processor with robust synchronization for high-speed WLAN applications, ¡§ in Digest of Technical Papers, Symposium on VLSI Circuits, Jun. 2004, pp. 156-159. [pdf] [EI] (MOEA 95-EC-17-A-03-S1-0005)

¤wµoªíµÛ§@ (·|ij½×¤å Conference Papers):

1.      Ching-Che Chung, Yu-Pei Liang, and Jo-Chen Huang, ¡§Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery,¡¨ in Proceedings of IEEE International Conference on Consumer Electronics ¡V Taiwan (ICCE-TW), Jul. 2023, pp. 133-134. [pdf] [EI] (MOST111- 2221-E-194-049-)

2.      Ching-Che Chung, Yu-Pei Liang, Ya-Ching Chang, and Chen-Ming Chang, ¡§A binary weight convolutional neural network hardware accelerator for analysis faults of the CNC machinery on FPGA,¡¨ in Proceedings of International VLSI Symposium on Technology, Systems and Applications (VLSITSADAT), Apr. 2023. [pdf] [EI] (MOST111- 2221-E-194-049-)

3.      Ching-Che Chung and Yi-Ting Tsai, ¡§A body channel communication transceiver with a 16x oversampling CDR and convolutional codes,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2022. [pdf] [EI] (MOST110-2221-E-194-045-)

4.      Ching-Che Chung, Huai-Xiang Zhang, Ming-You Hung, and Hong-Jin Jian, ¡§A DBN hardware accelerator for auditory scene classification,¡¨ in Proceedings of IEEE International Conference on Consumer Electronics ¡V Taiwan (ICCE-TW), Sep. 2020. [pdf] [EI] (MOST108-2221-E-194-051)

5.      Ching-Che Chung, Wei-Ting Chen, and Ya-Ching Chang, ¡§Using Quantization-Aware Training Technique with Post-Training Fine-Tuning Quantization to Implement a MobileNet Hardware Accelerator,¡¨ in Proceedings of 2020 Indo-Taiwan 2nd International Conference on Computing, Analytics and Networks (Indo-Taiwan ICAN), Feb. 2020, pp. 28-32. [pdf] [EI] (MOST108-2221-E-194-051)

6.      Ching-Che Chung and Hsin-Han Huang, ¡§An all-digital temperature sensor with process and voltage variation tolerance for IoT applications,¡¨ in Proceedings of 32nd IEEE International System-on-Chip Conference (SOCC), Sep. 2019, pp. 109-112. [pdf] [EI] (MOST108-2221-E-194-051)

7.      Ching-Che Chung, Wei-Jung Chu, and Yi-Ting Tsai, ¡§Built-in Self-Test Circuits for All-digital Phase-Locked Loops,¡¨ in Proceedings of IEEE International Conference on Consumer Electronics ¡V Taiwan (ICCE-TW), May. 2019. [pdf] [EI] (MOST107-2221-E- 194-031)

8.      Ching-Che Chung, Yi-Zeng Lee, and Huai-Xiang Zhang, ¡§Design of a DBN hardware accelerator for handwritten digit recognitions,¡¨ in Proceedings of IEEE International Conference on Consumer Electronics ¡V Taiwan (ICCE-TW), May. 2019. [pdf] [EI] (MOST107-2221-E-194-031)

9.      Ching-Che Chung, Wei-Jung Chu, and Yi-Ting Tsai, ¡§An all-digital built-in self-test circuit for ADPLLs in 65nm CMOS technology,¡¨ in Proceedings of 29th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2018. [pdf] (MOST106-2221-E-194-059)

10.  Ching-Che Chung, Ru-Hua Chang, and Ming-Hsuan Li, ¡§An FPGA-based transceiver for human body channel communication using Walsh Codes,¡¨ in Proceedings of IEEE International Conference on Consumer Electronics ¡V Taiwan (ICCE-TW), May. 2018. [pdf] [EI] (MOST106-2221-E-194-059)

11.  Ching-Che Chung, Dai-Hua Lee, and Yu-Hsin Wang, ¡§FPGA-based accelerator platform for K-means clustering algorithm,¡¨ in Proceedings of Annual Conference on Engineering and Applied Science (ACEAT), Nov. 2017, pp. 41-50. [pdf] (MOST106-2221-E-194-059)

12.  Ching-Che Chung and Yu-Hsin Wang, ¡§Hadoop cluster with FPGA-based hardware accelerators for K-means clustering algorithm,¡¨ in Proceedings of IEEE International Conference on Consumer Electronics ¡V Taiwan (ICCE-TW), Jun. 2017, pp. 143-144. [pdf] [EI] (MOST103- 2221-E-194-063-MY3) (Best Paper Award, Second Place)

13.  Ching-Che Chung, Yi-Che Tsai, and Ming-Chieh Li, ¡§A reference-less all-digital transceiver for human body channel communication,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2017. [pdf] [EI] (MOST103- 2221-E-194-063-MY3)

14.  Ching-Che Chung, Chih-Yu Lin, and Jia-Zong Yang, ¡§Time-domain characteristics of body channel communication (BCC) and BCC transceiver design,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2016. [pdf] [EI] (MOST103- 2221-E-194-063-MY3)

15.  Ching-Che Chung and Mei-I Sun, ¡§An all-digital voltage sensor for static voltage drop measurements,¡¨ in Proceedings of IEEE Sensors Applications Symposium (SAS), Apr. 2016. [pdf] [EI] (MOST103- 2221-E-194-063-MY3)

16.  Ching-Che Chung, Mei-I Sun, and Yi-Che Tsai, ¡§An all-digital on-chip voltage sensor for SoC design,¡¨ in Proceedings of 26th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2015. [pdf] (NSC102- 2221-E-194-063-MY3)

17.  Duo Sheng, Ching-Che Chung, Chia-Lin Wu, Sheng-Min Chan, and Min-Rong Hong, ¡§An all-digital and wide-range reference clock generator for biotelemetry applications,¡¨ in Proceedings of International Conference on Electronics and Software Science (ICESS), Jul. 2015, pp. 118-123. [pdf] (MOST103- 2221-E-030-025)

18.  Ching-Che Chung, Chen-Han Chen, and Chi-Kuang Lo, ¡§A DCO compiler for all-digital PLL design,¡¨ in Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Jun. 2015, pp. 543-546. [pdf] [EI] (NSC102- 2221-E-194-063-MY3)

19.  Ching-Che Chung, Chun-Kai Liu, and Dai-Hua Lee, ¡§FPGA-based accelerator platform for Big data matrix processing,¡¨ in Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Jun. 2015, pp. 221-224. [pdf] [EI] (NSC102- 2221-E-194-063-MY3)

20.  Ching-Che Chung, Chi-Tung Chang, and Chih-Yu Lin, ¡§A 1 Mb/s ¡V 40Mb/s human body channel communication transceiver,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2015. [pdf] [EI] (MOST103- 2221-E-194-063-MY3)

21.  Ching-Che Chung and Jhih-Wei Li, ¡§An all-digital on-chip abnormal temperature warning sensor for dynamic thermal management,¡¨ in Proceedings of 27th IEEE International System-on-Chip Conference (SOCC), Sep. 2014, pp. 221-224. [pdf] [EI] (NSC102- 2221-E-194-063-MY3)

22.  Ching-Che Chung, Chi-Tung Chang, Chuan-Yi Wu, Yu-Te Liao, and Chih-Yu Lin, ¡§A 1 Mb/s ¡V 40 Mb/s human body channel communication transceiver,¡¨ in Proceedings of 25th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2014. [pdf] (NSC102- 2221-E-194-063-MY3)

23.  Ching-Che Chung, Duo Sheng, and Chen-Han Chen, ¡§An all-digital phase-locked loop compiler with liberty timing files,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2014. [pdf] [EI] (NSC102- 2221-E-194-063-MY3)

24.  Ching-Che Chung and Chi-Yu Hou, ¡§All-digital delay-locked loop for 3D-IC die-to-die clock synchronization,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2014. [pdf] [EI] (NSC102- 2221-E-194-063-MY3)

25.  Ching-Che Chung, Shu-Xian Shen, Chuan-Yi Wu, Yu-Te Liao, and Chi-Tung Chang, ¡§A 1 Mb/s ¡V 40 Mb/s WBS transceiver for human body channel communication,¡¨ in Proceedings of 24th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2013. [pdf] (NSC101-2221-E-194-063)

26.  Duo Sheng, Ching-Che Chung, Chih-Chung Huang, and Jia-Wei Jian, ¡§A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications,¡¨ in Proceedings of 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Jul. 2013, pp. 2461-2464. [pdf] [EI] (NSC101-2221-E-030-025)

27.  Ching-Che Chung and Jhih-Wei Li, ¡§An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling,¡¨ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2013, pp. 2682-2685. [pdf] [EI] (NSC101-2221-E-194-063)

28.  Ching-Che Chung, Duo Sheng, and Wei-Siang Su, ¡§A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2013. [pdf] [EI] (NSC101-2221-E-194-063)

29.  Ching-Che Chung and Chang-Jun Li, ¡§A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2013. [pdf] [EI] (NSC101-2221-E-194-063)

30.  Ching-Che Chung and Ning-Mi Hsueh, ¡§A low-complexity high-performance wear-leveling algorithm for flash memory system design,¡¨ in Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2012, pp. 595-598. [pdf] [EI] (NSC100-2221-E-194-051)

31.  Ching-Che Chung, Duo Sheng, and Yang-Di Lin, ¡§An all-digital clock and data recovery circuit for spread spectrum clocking applications in 65nm CMOS technology,¡¨ in Proceedings of International Asia Symposium on Quality Electronic Design (ASQED), Jul. 2012, pp. 91-94. [pdf] [EI] (NSC100-2221-E-194-051)

32.  Duo Sheng, Ching-Che Chung, and Jhih-Ci Lan, ¡§A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications,¡¨ in Proceedings of International Asia Symposium on Quality Electronic Design (ASQED), Jul. 2012, pp. 123-127. [pdf] [EI] (NSC100-2221-E-030-012)

33.  Ching-Che Chung, Duo Sheng, and Wei-Da Ho, ¡§A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2012. [pdf] [EI] (NSC100-2221-E-194-051)

34.  Ching-Che Chung, Sung-En Shen and Wei-Da Ho, ¡§A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology,¡¨ in Proceedings of 22th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2011, pp. 380-383. [pdf] (NSC99-2220-E-194-011)

35.  Ching-Che Chung and Wei-Cheng Dai, ¡§A referenceless all-digital fast frequency acquisition full-rate CDR circuit for USB 2.0 in 65nm CMOS technology,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2011, pp. 217-220. [pdf] [EI] (NSC99-2220-E-194-011)

36.  Ching-Che Chung and Wei-Jung Chu, ¡§An all-digital on-chip jitter measurement circuit in 65nm CMOS technology,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2011, pp. 179-182. [pdf] [EI] (NSC99-2220-E-194-011)

37.  Ching-Che Chung, Chiun-Yao Ko and Sung-En Shen, ¡§A monotonic digitally controlled oscillator with self-calibration in 65nm CMOS technology,¡¨ in Proceedings of 21th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2010, pp. 327-330. [pdf] (NSC97-2218-E-194-009-MY2)

38.  Ching-Che Chung and Cheng-Ruei Yang, ¡§An all-digital smart temperature sensor with auto-calibration in 65nm CMOS technology,¡¨ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2010, pp. 4089-4092. [pdf] [EI] (NSC98-2220-E-194-013)

39.  Ching-Che Chung and Chia-Lin Chang, ¡§A wide-range all-digital delay-locked loop in 65nm CMOS technology,¡¨ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2010, pp. 66-69. [pdf] [EI] (NSC97-2218-E-194-009-MY2)

40.  Chia-Chi Hsiao, Hung-Ming Chen and Ching-Che Chung, ¡§Yield improvement in memory compiler generated SRAM with inter-die variations,¡¨ in Proceedings of 15th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2009), Mar. 2009, pp. 450-455. [pdf] (NSC97-2220-E-009-004)

41.  Duo Sheng, Ching-Che Chung and Chen-Yi Lee, ¡§An all digital spread spectrum clock generator with programmable spread ratio for SoC applications, ¡§ in Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2008, pp. 850-853. [pdf] [EI] (NSC96-2221-E-009-181)

42.  Jui-Yuan Yu, Juinn-Ting Chen, Mei-Hui Yang, Ching-Che Chung, and Chen-Yi Lee, ¡§An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems, ¡§ in Proceedings of 2007 IEEE International SOC Conference, Sep. 2007, pp. 305-308. [pdf] [EI] (MOEA 95-EC-17-A-03-S1-0005)

43.  Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, ¡§A fast-lock-in ADPLL with high-resolution and low-power DCO for SoC applications, ¡§ in Proceedings of 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2006, pp. 105-108. [pdf] [EI] (NSC95-2220-E-009-291)

44.  Jui-Yuan Yu, Ching-Che Chung, Hsuan-Yu Liu, and Chen-Yi Lee, ¡§Power reduction with dynamic sampling and all-digital I/Q-mismatch calibration for a MB-OFDM UWB baseband transceiver, ¡§ in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), Oct. 2006. [pdf] (MOEA 95-EC-17-A-03-S1-0005)

45.  Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, ¡§An all-digital phase-locked loop with high resolution for SoC applications, ¡§ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2006, pp. 207-210. [pdf] [EI] (NSC95-2220-E-009-291)

46.  Ching-Che Chung, Pao-Lung Chen, and Chen-Yi Lee, ¡§An all-digital delay-locked Loop for DDR SDRAM controller applications, ¡§ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2006, pp. 199-202. [pdf] [EI] (NSC93-2220-E-009-033)

47.  Pao-Lung Chen, Ching-Che Chung and Chen-Yi Lee, ¡§An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications, ¡§ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 4875-4878. [pdf] [EI]Summary: Not available..... (NSC93-2220-E-009-033)

48.  Hsie-Chia Chang, Ching-Che Chung, Chien-Ching Lin, and Chen-Yi Lee, ¡§A 300 MHz Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm, ¡§ in Proceedings of European Solid-State Circuits Conf. (ESSCIRC), Sep. 2002, pp. 519-522. [pdf] (NSC90-2218-E-009-035)

49.  Ching-Che Chung and Chen-Yi Lee, ¡§An all-digital phase-locked loop for high-speed clock generation, ¡§ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2002, pp.26-29. [pdf] [EI] (NSC90-2215-E-009-105)

50.  Ching-Che Chung and Chen-Yi Lee, ¡§A novel structure for portable digitally controlled oscillator, ¡§ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2001, pp.272-275. [pdf] [EI] (NSC90-2215-E-009-105)

51.  Yew-San Lee, Ching-Che Chung, Tsyr-Shiou Perng, Li-Chyun Hsu, Ming-Yang Jaw, and Chen-Yi Lee, ¡§A memory-based architecture for very high throughput variable length codec design, ¡§ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Jun. 1997, pp. 9-12. [pdf] [EI] (NSC86-2221-E-009-016)

¤wµoªíµÛ§@ (Ph.D. Dissertation):

³Õ¤h½×¤å¡G

À³¥Î©ó¨t²Î´¹¤ù³]­p¤§¦Û°Ê¤Æ¦X¦¨®É§ÇÂê¬Û°j¸ô

Automatic Synthesis of Timing-Locked Loops for SoC Designs [pdf]

±M§Q(Patents):

1.      Ching-Che Chung and Wei-Da Ho(¾Ç¥Í), ¡§All-digital spread spectrum clock generating circuit with EMI reduction effect and a method for controlling the same, ¡§ US patent 9,450,641 B2, Sep. 2016.

2.      Áéµ×­õ, ¦ó«Â¹F(¾Ç¥Í), ¡§¨ã¹qºÏ¤zÂZ®ÄÀ³°I´î¤§¥þ¼Æ¦ì®iÀW®É¯ß²£¥Í¹q¸ô¤Î¨ä±±¨î¤èªk, ¡§ ¤¤µØ¥Á°ê±M§Q²Ä I505642¸¹, ¥Á°ê104¦~.

3.      Áéµ×­õ, ¨H¹|®¦(¾Ç¥Í), ¡§¥þ¼Æ¦ì®É¯ß®Õ¥¿¹q¸ô¤Î¨ä¤èªk, ¡§ ¤¤µØ¥Á°ê±M§Q²Ä I448081 ¸¹, ¥Á°ê103¦~ 08 ¤ë 01 ¤é.

4.      Ching-Che Chung and Sung-En Shen(¾Ç¥Í), ¡§Full-digital Clock Correction Circuit and Method Thereof, ¡§ US patent 8,487,680 B1, Jul. 16, 2013.

5.      §õÂí©y, Áéµ×­õ, ¡§¥Î©ó¥þ¼Æ¦ìÂê¬Û°j¸ô³]­p¤§¼Æ¦ìÂoªi¾¹, ¡§ ¤¤µØ¥Á°ê±M§Q²Ä I360950 ¸¹, ¥Á°ê101¦~03¤ë21¤é.

6.      Chen-Yi Lee and Ching-Che Chung, ¡§ Digital Loop Filter for All-Digital Phase-Locked Loop Design, ¡§ US patent 7,696,832 B1, Apr.13, 2010.

ºtÁ¿°O¿ý(Speeches):

1.      ¡§¤¶²Ð¹s«H¥ô¸ê¦w(Zero Trust)ªºµwÅé¦w¥þ§Þ³N PUF (Physically Unclonable Function)¡¨, ¨p¥ß¨È¬w¤j¾Ç¸ê¹q¾Ç°|±MÃDÁ¿®y, 2022/12/08

2.      ¡§¤HÅé³q¹D¶Ç¦¬¾¹¡¨, °ê¥ß¹Å¸q¤j¾Ç¹q¾÷¨t, 2021/03/03

3.      ¡§¤HÅé³q¹D¶Ç¦¬¾¹¡¨, ¨p¥ß»²¤¯¤j¾Ç¹q¾÷¨t, 2020/06/17

4.      ¡§¥þ¼Æ¦ìÂê¬Û°j¸ô§Þ³N¤Î¨äÀ³¥Î¤¶²Ð¡¨, °ê¥ß¤¤¤s¤j¾Ç¹q¾÷¨t, 2016/10/04

5.      ¡§¥þ¼Æ¦ìÂê¬Û°j¸ô§Þ³N¤Î¨äÀ³¥Î¤¶²Ð¡¨, °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q³q¨t, 2016/03/24

6.      ¡§¸ê¤u¨t¾Ç¥ÍªºµwÅé³]­p¯à¤O°ö¾i¡¨,°ê¥ß«ÌªF¤j¾Ç¸ê¤u¨t, 2015/10/05

7.      ¡§All-Digital High-Speed Clock Generator and Thermal Sensor for Supporting DVFS in a Ultra-low-Power Processor¡¨, °ª¶¥À³¥Î³B²z¾¹APÁp·ù 2014 ¨t²Î´¹¤ù³]­p°ê»Ú¬ã²ß½Òµ{,°ê¥ß¥æ³q¤j¾Ç, 2014/08/13

8.      ¡§¼Æ¦ì¹q¸ô¯à®³¨Ó§@¤°»ò?¡¨, °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¤l¨t, 2013/03/14

9.      ¡§¼Æ¦ì¹q¸ô¯à®³¨Ó§@¤°»ò?¡¨, ¨p¥ß»²¤¯¤j¾Ç¹q¾÷¨t, 2011/11/02

10.  ¡§All-Digital PLL Design¡¨,°ê¥ß¶³ªL¬ì§Þ¤j¾Ç¹q¾÷¨t, 2010/04/09.

11.  ¡§Low-Power SoC Physical Design¡¨,°ê¥ß¤¤¥¿¤j¾Ç¸ê¤u¨t, 2008/03/07.

12.  ¡§Low-Power SoC Design¡¨,°ê¥ß¦¨¥\¤j¾Ç¹q¾÷¨t, 2007/09/27.

13.  ¡§All-Digital PLL/DLL Design and Its Applications¡¨,°ê¥ß¥æ³q¤j¾Ç¹q«H¨t, 2007/05/24.

14.  ¡§All-Digital PLL Design¡¨, ¿Ë¥Á§Þ³N¾Ç°|¹q¤l¨t, 2005/05/04.

S3 LAB¾Ç¥Í²¦·~½×¤å(S3 LAB Dissertations) :

¶µ¥Ø

¾Ç¦~«×

©m¦W

½×¤åÃD¥Ø

1

98

¬_¶vÄ£

§Ö³t¬Û¦ì°lÂÜ»P°ªÀW²v­¿¼Æ¥þ¼Æ¦ìÂê¬Û°j¸ô³]­p»PÀ³¥Î

Fast Phase Tracking and High Frequency Multiplication Factor All-Digital Phase-Locked Loop and Its Applications. [pdf]

2

98

±i¹ÅÅï

¾A¥Î¼eÀW¾Þ§@¤§¥þ¼Æ¦ì©µ¿ðÂê¬Û°j¸ô

A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS technology. [pdf]

3

98

ᬩ

¥þ¼Æ¦ì¦Û°Ê®Õ¥¿´¼¼z«¬·Å«×°»´ú´¹¤ù

All-Digital Smart Temperature Sensor with Self-Calibration in 65nm CMOS Technology. [pdf]

4

99

À¹°¶¥à

¥iÀ³¥Î©ó USB 2.0 ¤§µL°Ñ¦Ò®É¯ß¥þ¼Æ¦ì§Ö³tÂê©w¤§³sÄò³t²v¸ê®Æ»P®É¯ß¦^´_¹q¸ô

An Referenceless All-Digital Fast Frequency Acquisition Full-Rate Continuous Rate CDR Circuit for USB 2.0 in 65nm CMOS Technology. [pdf]

5

99

¦¶Á¨»T

À³¥Î©ó¥þ¼Æ¦ìÂê¬Û°j¸ô¤§¦Û§Ú´ú¸Õ¹q¸ô³]­p

Design of All-Digital Built-In Self-Test Circuit for All-Digital Phase-Locked Loops. [pdf]

6

99

¨H¹|®¦

À³¥Î©ó¼eÀW¾Þ§@¤§¥þ¼Æ¦ì®É¯ß³d¥ô¶g´Á®Õ¥¿»P¿é¥X¬Û¦ì¹ï»ô¹q¸ô

A Wide-Range All-Digital Duty-Cycle Corrector with Output Clock Phase Alignment in 65nm CMOS Technology. [pdf]

7

99

±i®a»Ê

À³¥Î©ó°ÊºA¨t²Î®Ä¯à½Õ¾ã¤§´O¤J¦¡·Å«×»P¹q¸ô©µ¿ð·P´ú¾¹»P¨t²ÎÅçÃÒ§Þ³N¶}µo

On-Chip Temperature and Delay Sensors for Adaptive System Design and System Verification with SVA. [pdf]

8

100

Á§Ú¬ÁÄ

¥iÀ³¥Î©ó§Ö°{°O¾ÐÅé¨t²Î³]­p¤§°ª®Ä¯à¤Î§C½ÆÂø«×¥­­±¤Æºtºâªk

A Low-Complexity High-Performance Wear-Leveling Algorithm for Flash Memory System Design. [pdf]

9

100

´­­}

À³¥Î©ó®iÀW§Ç¦C³q°T¤§¥þ¼Æ¦ì¸ê®Æ¦^´_¹q¸ô

An All-Digital Clock and Data Recovery Circuit for Spread Spectrum SerDes Applications. [pdf]

10

100

³\µqµ¾

¥iÀ³¥Î©ó§ïµ½©TºAµwºÐºÏºÐ°}¦C¤§¦s¨ú®Ä¯àªº¦P¦ì¤¸Àˬd½X¤Î¸ê®Æªº§Ö¨úºÞ²z¾÷¨î

A Parity Check and Data Cache Management Method to Improve the Performance of a Solid-State Disk-Based RAID. [pdf]

11

100

¦ó«Â¹F

¨ã¦³·¥¨Îªº¹qºÏ¤zÂZ®ÄÀ³°I´î®ÄªG¤§¥þ¼Æ¦ì®iÀW®É¯ß²£¥Í¾¹

Design of All-Digital Spread-Spectrum Clock Generator with High EMI Reduction. [pdf]

12

101

§õ»x°¶

¨Ï¥Î¼Ð·ÇÅ޿褸¥ó³]­p¨Ã¥i¸ÉÀv»sµ{¹qÀ£¤Î·Å«×Åܲ§¹ï¿é¥XÀW²v¼vÅT¤§´O¤J¦¡ª¿®¶Àú¾¹

A cell-based on-chip silicon oscillator for frequency compensation with PVT variations. [pdf]

13

101

§õªø¼í

¥i¤u§@©ó 0.5V/1.0V¨Ã¨ã¦³«D¹ïºÙ»sµ{ÄƲ¾®e§Ô«×¤§§C¥\¯Ó©µ¿ð½u­«½Æ§Q¥Î¥þ¼Æ¦ì³d¥ô¶g´Á®Õ¥¿¹q¸ô

A 0.5V/1.0V low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance. [pdf]

14

101

ĬÞmµ¾

¥i¤ä´©°ÊºA¹qÀ£»PÀW²v½Õ¾ã¤§§Ö³tÂê©w 0.5V/1.0V ¥þ¼Æ¦ìÂê¬Û°j¸ô³]­p

A 0.5V/1.0V fast lock-in ADPLL for supporting dynamic voltage and frequency scaling. [pdf]

15

101

¨H®Ñ½å

1Mbps ¡V 40Mbps ¤HÅé³q¹D¶Ç¦¬¾¹³]­p

Design of 1 Mbps ¡V 40 Mbps human body channel communication transceiver. [pdf]

16

102

³¯­s¿«

¶}µo©`¦Ì»sµ{¤U¤§¥þ¼Æ¦ìÂê¬Û°j¸ô¦Û°Ê²£¥Í¾¹

Develop an all-digital phase-locked loop compiler in nanometer CMOS technologies. [pdf]

17

102

±i´Ñ´É

1Mbps¡V 40Mbps ¤HÅé³q¹D¶Ç¦¬¾¹³]­p»P¹ê²{

Design and Implementation of a 1 Mbps ¡V 40 Mbps human body channel communication transceiver. [pdf]

18

102

«J¬ö¦t

À³¥Î©ó¤Tºû´¹¤ù®É¯ß¦P¨B¤§¥þ¼Æ¦ì©µ¿ðÂê¬Û°j¸ô

An all-digital delay-locked loop for 3D ICs die-to-die clock synchronization. [pdf]

19

102

¼B«T³Í

¶}µo»P¹ê²{¥iÀ³¥Î©ó¥¨¶q¸ê®Æ¤ÀªR¤§FPGA µwÅé¥[³t¥­¥x

Development and Implementation of an FPGA-based hardware accelerator for big data analysis. [pdf]

20

103

ªL­P¦ö

¤HÅé³q¹D¶Ç¿é¯S©Ê»P³]­p¤HÅé³q¹D¶Ç¦¬¾¹

Characteristics of the human body channel and design the human body channel transceiver. [pdf]

21

103

§õ©§¾ì

¥Î©ó¸ê®Æ±K¶°«¬¹Bºâ¤§°ªÂX®i©ÊFPGA µwÅé¥[³t¥­¥x

High Scalability FPGA-based hardware accelerator for data-intensive computation. [pdf]

22

103

ù±Ò¥ú

40 ©`¦Ì»sµ{¤U¶}µo»P³]­p§Ö³tÂê©w¤§¥þ¼Æ¦ìÂê¬Û°j¸ô

Design of A Fast Lock-In All-Digital Phase-Locked Loop in 40-nm CMOS technology. [pdf]

23

103

®]¬ü©É

¨Ï¥Î¼Ð·ÇÅ޿褸¥ó¤Î¬Û¹ï¦¡°Ñ¦Ò¼Ò«¬§Þ³N³]­p¤§ÀRºA¹qÀ£À£­°°»´ú¾¹»P´O¤J¦¡ª¿®¶Àú¾¹

Design of a static IR-drop monitor and an on-chip silicon oscillator with cell-based and relative reference modelling approaches. [pdf]

24

104

½²©y­õ

¥iÀ³¥Î©ó¤HÅé³q¹D¶Ç¿é¤§µL°Ñ¦Ò®É¯ß¥þ¼Æ¦ì¸ê®Æ»P¦^´_¹q¸ô³]­p

A Reference-Less All-Digital CDR Circuit for Human Body Channel Communication. [pdf]

25

104

¤ý«Éªä

«Øºc©ó¥iµ{¦¡¤ÆÅÞ¿èªO¹ê²{µwÅé¥[³t¤§Hadoop ÂO¶°¥Î©ó¸ê®Æ±´°Éºtºâªk

Hadoop Cluster with FPGA-based Hardware Accelerators for Data Mining Algorithms. [pdf]

26

104

·¨¨Îºa

«Øºc©ó¥iµ{¦¡ÅÞ¿èªO¤§¤HÅé³q¹D¶Ç¿é¦¬µo¾¹³]­p

An FPGA-based Transceiver for Human Body Channel Communication Applications. [pdf]

27

105

§õ»Ê³Ç

¥iÀ³¥Î©ó¤HÅé³q¹D¶Ç¿é¥B¨ã¦³§Ö³t¬Û¦ì°lÂÜ¥\¯àªºµL°Ñ¦Ò®É¯ß¥þ¼Æ¦ì¸ê®Æ»P¦^´_¹q¸ô³]­p

Fast Phase Tracking Reference-Less All-Digital CDR Circuit for Human Body Channel Communication. [pdf]

28

105

±i¯øµØ

¨Ï¥ÎµØ¤ó½X¨Ã«Øºc©ó¥iµ{¦¡ÅÞ¿èªO¤§¤HÅé³q¹D¶Ç¿é¦¬µo¾¹

An FPGA-based Transceiver for Human Body Channel Communication using Walsh Codes. [pdf]

29

106

§õ«³¼W

¥Î©ó¤â¼g¼Æ¦r¿ëÃѪºDBNµwÅé¥[³t¾¹³]­p

Design of a DBN hardware accelerator for handwritten digit recognition. [pdf]

30

106

¶À«H¿«

¤@­Ó¾A¥Î©óª«ÁpºôÀ³¥Î¨Ã¥i©è§Ü»sµ{»P¹qÀ£Åܲ§ªº¥þ¼Æ¦ì·Å«×·P´ú¾¹

An All-digital Temperature Sensor with Process and Voltage Variations Tolerance for IoT Applications. [pdf]

31

106

§õ»Ê°a

¨Ï¥Î¨÷¿n½X¨Ã«Øºc©ó¥iµ{¦¡ÅÞ¿èªO¤§¤HÅé³q¹D¶Ç¿é¦¬µo¾¹¤§³]­p»P¹ê²{

Design and Implementation of a Human Body Channel Communication Transceiver on FPGA Using Convolutional Codes. [pdf]

32

107

¬x°ê®i

K-means ºtºâªkµwÅé¥[³t¾¹ªº³]­p©M¹ê²{

Design and implementation of a hardware accelerator for K-means algorithm. [pdf]

33

107

±i²aµ¾

¨Ï¥ÎK-means ºtºâªk¥Î©ó°V½m«á¶q¤Æ¨Ó¹ê²{¥Î©óťı³õ´º¤ÀÃþªºDNNµwÅé¥[³t¾¹

A DNN Hardware Accelerator for Auditory Scene Classification Using the K-means Clustering Algorithm in Post-Training Quantization. [pdf]

34

107

½²©y®x

¨Ï¥Î¤Q¤»­¿¶W¨ú¼Ë®É¯ß»P¸ê®Æ¦^´_¹q¸ô¤Î¨÷¿n½Xªº¤HÅé³q¹D¶Ç¿é¦¬µo¾¹

A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes. [pdf]

35

107

³¯«Â§Ê

¨Ï¥Î¶q¤Æ·Pª¾°V½m§Þ³N·f°t°V½m«á·L½Õ¶q¤Æ¨Ó¹ê²{ MobileNet µwÅé¥[³t¾¹

Using Quantization-Aware Training Technique with Post-Training Fine-Tuning Quantization to Implement a MobileNet Hardware Accelerator. [pdf]

36

108

¶À­Yºd

¨Ï¥Î¤T¤¸¶q¤Æ¤èªk¹ê²{¤§»´¶q¯Å¨÷¿n¯«¸gºô¸ôµwÅé¥[³t¾¹¥Î©óCNC¤u¨ã¾÷§Y®É¬G»Ù¶EÂ_

Lightweight Convolutional Neural Network Hardware Accelerator Using the Ternary Quantization Method for Real-Time Fault Diagnosis of CNC Machinery. [pdf]

37

108

·¨¶{Öo

¨Ï¥Î»¼°j¤èªk©è§Ü»sµ{¡B¹qÀ£»P·Å«×Åܲ§ªº¶°¦¨¦¡¹qÀ£»P·Å«×·P´ú¾¹

Integrated Voltage and Temperature Sensors that Use Recursive Methods to Resist Process, Voltage, and Temperature Variations. [pdf]

38

108

±i¶®´¸

¨Ï¥ÎFPGA¹ê²{¤§¤G¤¸¤Æ¨÷¿n¯«¸gºô¸ôµwÅé¥[³t¾¹À³¥Î©ó CNC ¤u¨ã¾÷¬G»Ù¤ÀªR

A Binary Weight Convolutional Neural Network Hardware Accelerator for Analysis Faults of the CNC Machinery on FPGA. [pdf]

39

108

¬x»Ê¦ö

¥Î©óCNC ¤u¨ã¾÷§Y®É¶b©Óª¬ºAÀË´ú¤§µL­¼ªk¾¹¨÷¿n¯«¸gºô¸ôµwÅé¥[³t¾¹

A multiplier-free convolution neural network hardware accelerator for real-time bearing condition detection of CNC machinery. [pdf]

40

109

³¯¶h¦|

¨Ï¥Îº|¹q¬y¤¸¥ó«Ø¥ßªº¶°¦¨¦¡¹qÀ£»P·Å«×·P´ú¾¹¨Ã¯à©è§Ü»sµ{¡B¹qÀ£»P·Å«×Åܲ§

Integrated voltage and temperature sensors built with leakage current components and resistant to process, voltage and temperature variations. [pdf]

41

109

²§»®Ê

°ò©ó¹q¬y°T¸¹ªº¶b©Ó¬G»Ù¶EÂ_¨Ï¥Î¤@ºû¨÷¿n¯«¸gºô¸ô¨Ã©óFPGA¹ê²{

A one-dimensional convolutional neural network implemented on FPGA for bearing fault diagnosis based on the current signals. [pdf]

42

109

±i¼z¸©

³q¹L¤ÀªR¹q¬y°T¸¹¶i¦æ¶b©Ó¬G»Ù¶EÂ_¤§§C¥\¯Ó¨÷¿n¯«¸gºô¸ô¨Ï¥Î40 ©`¦Ì»sµ{¹ê²{

A low-power convolutional neural network implemented in 40-nm CMOS technology for bearing fault diagnosis by analyzing current signals. [pdf]

43

109

´^¸Ö²[

¶}µo¥i¦³®Ä©è§Ü¾÷¾¹¾Ç²ßªºª«²z¤£¥i½Æ»s¨ç¼Æ©M¥þ¼Æ¦ìÂê¬Û°j¸ôªº¦P¨B®ÉÄÁ°ì¬ã¨s

Development of a Physical Unclonable Function (PUF) that can effectively resist machine learning and an ADPLL clock domain synchronization research. [pdf]

44

110

¬x¨Î°¶

¨Ï¥Î¦Û§Ú®Õ¥¿ªº¼Æ¦ì±±¨î®¶Àú¾¹¥Î©ó¶°¦¨¦¡¹qÀ£»P·Å«×·P´ú¾¹¨Ã¯à©è§Ü»sµ{¡B¹qÀ£»P·Å«×Åܲ§

Use self-calibrating digitally controlled oscillators for integrated voltage and temperature sensors and are resistant to the process, voltage, and temperature variations. [pdf]

45

110

³¯«~¾ì

¨÷¿n¯«¸gºô¸ôµwÅé¥[³t¾¹ªº§Ö³t³]­p¬yµ{¬ã¨s¨Ã©óFPGA¹ê²{

Research on the rapid design process of a hardware accelerator for convolutional neural networks and its implementation on FPGA. [pdf]

46

110

·Å«T¿Î

¶}µo°ª¥i¾a«×¥B¹ï¾÷¾¹¾Ç²ß§ðÀ»¨ã¦³±j¤j©è§Ü¤Oªºª«²z¤£¥i½Æ»s¨ç¼Æ(PUF)

Develop highly reliable physically unclonable functions (PUFs) with robust resistance to machine learning attacks. [pdf]

47

110

³¯ÅV

¦bFPGA¤W¹ê²{¥Î©ó¶b©Ó¬G»Ù¶EÂ_ªº¤@ºû²`«×¥i¤ÀÂ÷¨÷¿n¯«¸gºôµ¸

A one-dimensional depthwise separable convolutional neural network for bearing fault diagnosis implemented on FPGA. [pdf]

48

110

³\³óµÏ

±Ä¥Î 40 ©`¦Ì»sµ{¹ê²{¤§¥Î©ó¶b©Ó¬G»Ù¶EÂ_ªº§C¥\¯Ó¤À¼h¨÷¿n¯«¸gºô¸ôµwÅé¥[³t¾¹

A low-power hierarchical convolutional neural network hardware accelerator implemented in 40-nm CMOS technology for bearing fault diagnosis. [pdf]

49

110

¸â¤Wæf

À³¥Î©ó²`«×«H©Àºô¸ôªºS«¬¨ç¼Æ¤§°ª®Ä²vµwÅé¹ê²{

Efficient hardware implementation of Sigmoid function in deep belief networks. [pdf]

50

111

ÄÁ±á¤ß

¶}µo»P³]­p¹ê²{°w¹ïÁp¨¹¦¡¾Ç²ß¤§¨÷¿n¯«¸gºô¸ô°V½mªºµwÅé¥[³t¾¹

Development and Design of a Hardware Accelerator for Convolutional Neural Network Training in Federated Learning. [pdf]

51

111

¤ý´ðºð

³]­p»PÀu¤Æ¨Ï¥Î40nm CMOS»sµ{¹ê²{ªº§Ö³tÂê©w¥þ¼Æ¦ìÂê¬Û°j¸ô

Design and Optimization of Fast-Lock All-Digital Phase-Locked Loop Implemented using 40nm CMOS Process. [pdf]

52

111

¶À­³µ¾

°ò©óÁôÂìD¾Ô¦^À³°t¹ï¾÷¨î¨Ã¹ï¾÷±ñ¾Ç²ß®i²{±j¤Æ©è§Ü¤Oªºª«²z¤£¥i½Æ»s¨ç¼Æ¶}µo

Development of Physically Unclonable Functions (PUFs) Based on Hidden Challenge-Response Pair Mechanisms with Enhanced Resistance to Machine Learning. [pdf]

53

111

±i®f»Ê

§Q¥Î40©`¦Ì»sµ{¹ê²{±a¦³´£«e°h¥X¾÷¨îªº»´¶q¯Å¨÷¿n¯«¸gºô¸ô©óµL¤H­¸¦æ¸ü¨ã¤õ¨a°»´ú¤§À³¥Î

Implementation of Lightweight Convolutional Neural Networks with Early Exit Mechanism Utilizing 40nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles. [pdf]

54

111

¶À²Ð°a

³]­p»P¹ê²{40©`¦ÌCMOS»sµ{ªºPAM-4±µ¦¬¾¹»Pµ¥¤Æ¾¹¬ã¨s

Development and Implementation of PAM-4 Receiver and Equalizer Using 40-nm CMOS Process. [pdf]

ªA°È(Services) :

¨t©e­û(¸ê°T¤uµ{¾Ç¨t)

1.      ¾á¥ô¤j¾Ç³¡¨Æ°È¤p²Õ©e­û

a.          ¨ó§U¤j¾Ç³¡ºÂ¸Õ©Û¥Í¨Æ©y

b.          ¨ó§U³W¹º¤j¾Ç³¡½Òµ{³W¹º

c.           ¨ó§U³W¹º¾Ç¤h¯Z·s¥Í­×·~³W©w

d.          ¾á¥ô¯Z¾É®v

2.      ¾á¥ô¬ã¨s©Ò¨Æ°È¤p²Õ©e­û

3.      ¾á¥ô¨t°Èµo®i©e­û·|©e­û

a.          ¨ó§U¶i¦æ IEET ¤uµ{¤Î¬ì§Þ±Ð¨|»{ÃÒ

b.          ¨ó§U¶i¦æ½Òµ{ÀË°Q»P®Ö¤ß¯à¤O²Î­p

4.      ¾á¥ô¸g¶O³]³Æ¤p²Õ©e­û

a.          ¨ó§U³Ð·s¤j¼Ó·s¼WªÅ¶¡³W¹º

b.          ¨t¤WªÅ¶¡¨Ï¥Î¤À°t³W¹º

c.           ¨t¤W¸g¶O¨Ï¥Î¤À°t³W¹º

d.          ¨t¤W 501 ±Ð¾Ç¹êÅç«ÇSUN/Linux ¤u§@¯¸ºÞ²z»PºûÅ@

e.           ¨t¤W 206 ¹q¸£±Ð«Ç¸g¶O»P±ÄÁʶµ¥Ø³W¹º

5.      ¾á¥ô½Òµ{©e­û·|©e­û

6.      ¾á¥ô©Û¥Í©e­û·|©e­û

7.      ¾á¥ô¾Ç¤h¯ZºÂ¿ï¤J¾Ç¼f¬d¤Î¤f¸Õ©e­û

8.      ¾á¥ôºÓ¤h¯ZºÂ¸Õ¼f¬d¤Î¤f¸Õ©e­û

9.      ¾á¥ôºÓ¤h¯Z©Û¥Í©RÃD¤Î¾\¨÷©e­û

10.  ¾á¥ô³Õ¤h¯Z©Û¥Í¼f¬d¤Î¤f¸Õ©e­û

11.  ¾á¥ô³Õ¤h¯ZºÂ¸Õ¼f¬d¤Î¤f¸Õ©e­û

12.  ¾á¥ô³Õ¤h¯Z¸ê®æ¦Ò©RÃD©e­û

 

®Õ©e­û

1.      ¾á¥ô±Ð¾Ç·N¨£½Õ¬d©e­û·|©e­û¤u¾Ç°|¥Nªí

 

¨ä¥LªA°È¨ÆÂÝ

1.      ½×¤å¼f¬d©e­û

a.          ´Á¥Z

u  IEEE Journal of Solid-State Circuits (JSSC)

u  IEEE Transactions on Circuits and Systems I&II (TCAS-I, II)

u  IEEE Transactions on VLSI Systems (TVLSI)

u  IEEE Signal Processing Letters (SPL)

u  Journal of VLSI Signal Processing

u  International Journal of Electrical Engineering (IJEE)

b.          ¬ã°Q·|

u   Technical Program Committee (TPC) for IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT 2012 - 2018)

u   Technical Program Committee (TPC) for IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004)

u   University Design Contest Committee for Asia and South Pacific Design Automation Conference (ASP-DAC 2010)

u   Session Chair for IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT 2010 - 2014)

u   Session Chair (PLL/DLL) for 2010 VLSI Design/CAD Symposium

u   IEEE Solid-State Circuits Conference (ISSCC)

u   IEEE Asian Solid-State Circuits Conference (A-SSCC)

u   IEEE Symposium on Circuits and Systems (ISCAS)

u   IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

u   Design, Automation & Test in Europe (DATE)

2.      ºÓ³Õ¤h¾Ç¦ì¤f¸Õ©e­û

u  (96 ¾Ç¦~«×) °ê¥ß¥æ³q¤j¾Ç¹q¤l©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G±iÖq¯ø¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©óµø°T¨t²Î¤§§Ö³t¬Û¦ì°lÂÜ»P°ªÀW²v­¿¼Æ¥þ¼Æ¦ì¦¡Âê¬Û°j¸ô¡v

u  (96 ¾Ç¦~«×) °ê¥ß¥æ³q¤j¾Ç¹q¤l©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G³¯«T§Ê¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©óµL½uªñ¨­ºô¸ô¤§¥i½Õ¦¡¥þ¼Æ¦ì®É¯ß²£¥Í¾¹¡v

u  (96 ¾Ç¦~«×) °ê¥ß¥æ³q¤j¾Ç¹q¤l©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G¶À¤W»«¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©óµL½uªñ¨­ºô¸ô¤§´O¤J¦¡´¹Åé¾_Àú¾¹¡v

u  (97 ¾Ç¦~«×) °ê¥ß¥æ³q¤j¾Ç¹q¤l©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G¿à¬R¦|¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©ó SVC µø°T½s½X¼Ð·Ç¤§ªÅ¶¡¥i¾AÀ³©Ê¤º´V¸Ñ½X¾¹³]­p¡v

u  (97 ¾Ç¦~«×) °ê¥ß¥æ³q¤j¾Ç¹q¤l©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G°¨¾å²[¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©ó¥¿¥æ¤ÀÀW¦h¤u§Þ³N¬°°ò¦¤§µL¥Û­^µL½u¶i¨­ºô¸ô¦P¨B¾¹¡v

u  (97 ¾Ç¦~«×) °ê¥ß¥æ³q¤j¾Ç¹q¾÷¾Ç°| IC ³]­p²£·~¬ãµoºÓ¤h¯Z¡A¾Ç¥Í¡G·¨´¼¶W¡A½×¤åÃD¥Ø¡G¡u´O¤J¦¡´¹Åé¾_Àú¾¹¤§®É¯ß²£¥Í¾¹³]­p¡v

u  (97 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G¼B«T¨j¡A½×¤åÃD¥Ø¡G¡u¦h¬Û¦ì¼Æ¦ìÂê¬Û°j¸ô¹q¸ô³]­p¡v

u  (97 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡GªLÚzµ¾ ¡A½×¤åÃD¥Ø¡G¡u¼Æ¦ì±±¨î¦h¬Û¦ì©µ¿ðÂê©w°j¸ô¨Ï¥Î§ï¨}«¬®Õ·Ç§Þ³N¡v

u  (98 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡GĬ«G¦m¡A½×¤åÃD¥Ø¡G¡u±Ä¥Î¦@¦Pªí®æ¤À³Îµ¦略¤§¦h¼Ò¦¡æi½s¸Ñ½X¾¹¡v

u  (98 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G±ç¯q¸à¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©ó°ªµe½è¹qµø¤§H.264/AVSÂù­«¼Ò¦¡°ÊºA¸ÉÀv¨t²Î³]­p¡v

u  (98 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G³\¹äÄõ¡A½×¤åÃD¥Ø¡G¡u°ò©ó´ú¸Õ¦s¨ú¾÷¨î¤§«D¶°¤¤¦¡°£¿ù¬[ºc¤º¦h®Ö¤ß°£¿ù»²§U³B²z¾¹¡v

u  (98 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G¾G°a³Õ¡A½×¤åÃD¥Ø¡G¡u¥H FPGA ¹ê²{µL¤@­P©Ê§Ö¨ú°O¾ÐÅé°ò©óÀô§Î¬[ºc´¹¤ùºô¸ô¦h®Ö¤ß¨t²Î¡v

u  (98 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G³¢¤h»ô¡A½×¤åÃD¥Ø¡G¡u§Q¥Î®É¶¡¸Ñ½X¾¹¤Î®É¶¡°½¨ú§Þ³N¤§¥i½Õ©Ê¦h¶g´Á³B²z¾¹¡v

u  (98 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G½²ªø§»¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©ó H.264/SVC/Multi-View µø°T½s½X¤§¥i¤ä´©°ÊºA·j´M½d³ò²¾°Ê¹w´úª¿´¼°]³]­p¡v

u  (98 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G·¨­P¥þ¡A½×¤åÃD¥Ø¡G¡u¨ã°ÊºA¼Ò¦¡¿ï¾Ü¤§¤À¼Æ«¬²¾°Ê¦ô´úª¿´¼°]³]­p¡v

u  (98 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G±i¹D«°¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©ó´O¤J¦¡¥­¥x¤U¤§§C½ÆÂø«×¼v¤ùº[¼v¹³±µ¦Xºtºâªk¡v

u  (98 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G§õÄÉ©É¡A½×¤åÃD¥Ø¡G¡u¥­¦æ¤Æ¥i½Õ¦¡ H.264 ¸Ñ½X¾¹¬[ºc³]­p¡v

u  (99 ¾Ç¦~«×) ¥æ³q¤j¾Ç¹q¾÷¾Ç°|·L¹q¤l©`¦Ì¬ì§Þ²£·~¬ãµoºÓ¤h¯Z¡A¾Ç¥Í¡G³¢®É©ú¡A½×¤åÃD¥Ø¡G¡u¥H®É¶¡Âà´«¼Æ¦ì¬°°ò¦¤§§C¦¨¥»·Å«×·P´ú¾¹³]­p¡v

u  (99 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G¤ý¤l²»¡A½×¤åÃD¥Ø¡G¡u¦h¬Û¦ì¦Û§Ú®Õ·Ç¤§­«ÂйGªñ¼È¦s¾¹©µ¿ðÂê©w°j¸ô¡v

u  (99 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡Gªô«T¿«¡A½×¤åÃD¥Ø¡G¡u¦h¬Û¦ì¨ã¦³ºÊ±±­p¼Æ¤§¥þ¼Æ¦ìÂê¬Û°j¸ô¡v

u  (99 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G©P®Ñ¥È¡A½×¤åÃD¥Ø¡G¡u§C¥\²v¦h®Ö¤ß´¹¤ù³]­p¤§ÃöÁä¬[ºcÀu¤Æ¡v

u  (100 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¹q¾÷¤uµ{¬ã¨s©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G¸­ªø«C¡A½×¤åÃD¥Ø¡G¡u§Q¥Î¹w¥ý³ê¿ô¦¡¹q·½¹h±±µ¦²¤©ó³B²z¾¹¥\¯à³æ¤¸¥H¹F¨ì§C¥\²v­pºâ¨Ãºû«ù®Ä¯à¤§¬ã¨s¡v

u  (100 ¾Ç¦~«×) °ê¥ß¥æ³q¤j¾Ç¹q¤l»P¥ú¹q¾Çµ{ºÓ¤h¯Z¡A¾Ç¥Í¡G´å¨Î¿Ä¡A½×¤åÃD¥Ø¡G¡u¨ã¦³¥æ¿ù«¬¿ðº¢©µ¿ð¤¸¥óªº§C¥\¯Ó¼Æ¦ì±±¨î¾_Àú¾¹¡v

u  (101 ¾Ç¦~«×) °ê¥ß¥æ³q¤j¾Ç¹q¤l©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G§º°¶»¨¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©óµL½uªñ¨­ºô¸ô¤§§C¯Ó¯à°òÀW³B²z¾¹³]­p¡v

u  (101 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G²°ê¦w¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©ó¥ßÅéµø°T°õ¦æºüºÞ½u¥­¦æ¤§ÅçÃÒ·Pª¾³]­p¤èªk¡v

u  (101 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G³¯§ÊÂ`¡A½×¤åÃD¥Ø¡G¡uLFSR ¨ãÀH¾÷Àx¦s¸Ë¸m¤§¬ã¨s¡v

u  (101 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡GªL¤T²»¡A½×¤åÃD¥Ø¡G¡u¥þ¼Æ¦ìÂê¬Û°j¸ô¹B¥Î LFSR ¤Î­¸¥[¾¹¤§¬ã¨s¡v

u  (101 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G¾G©_ªY¡A½×¤åÃD¥Ø¡G¡uµêÀÀÀH¾÷¦sÀx¬[ºcµ²¦X­¸¥[¾¹ÀW²v¦X¦¨¾¹¤§¹ê²{»P¤ÀªR¡v

u  (101 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¤l¤uµ{¨tºÓ¤h¯Z¡A¾Ç¥Í¡G¼B¯Õ§Ó¡A½×¤åÃD¥Ø¡G¡u°ò©ó¯ß½ÄÁY´î»P¯ß½ÄÂX¼W¤§°ª¸ÑªR«×¤¬¸É¦¡ª÷®ñ¥b®É¶¡¦Ü¼Æ¦ìÂà´«¾¹¡v

u  (101 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¤l¤uµ{¨tºÓ¤h¯Z¡A¾Ç¥Í¡GªL¥@»¨¡A½×¤åÃD¥Ø¡G¡u¨ã¦±²v®Õ¥¿¤Î³æÂI®Õ¥¿¤ä´©¤§¥þ¼Æ¦ì´¼¼z«¬·Å«×·P´ú¾¹¤§³]­p»P¹ê§@¡v

u  (102 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¹q¾÷¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G§d»Í¯q¡A½×¤åÃD¥Ø¡G¡u¤Ï¬Û¤Î¦P¬Ûª`¤J½¢¦X C¯Å®¶Àú¾¹¤§³]­p»P¤ñ¸û¡v

u  (102 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¹q¾÷¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G³\¥°ª@¡A½×¤åÃD¥Ø¡G¡u§C¥\²v¹q¬y¦@§Q¥Î¤§ÂùÀW±a±µ¦¬¾÷³]­p¡v

u  (102 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G§õ°¶¹Å¡A½×¤åÃD¥Ø¡G¡u¥þ¼Æ¦ìÂê¬Û°j¸ô¨ã°ÊºAÀW²v­p¼Æ¤§¬ã¨s¡v

u  (102 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G§õ¤j¦¨¡A½×¤åÃD¥Ø¡G¡uµêÀÀÀH¾÷¦sÀxÀ³¥Î¤§¬ã¨s¡v

u  (102 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¸£»P³q°T¤uµ{©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G§d©Ó¬x¡A½×¤åÃD¥Ø¡G¡u­¸¥[¾¹»P LFSR ÀH¾÷¦sÀx¸Ë¸m¤§¬ã¨s¡v

u  (102 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¤l¤uµ{¨tºÓ¤h¯Z¡A¾Ç¥Í¡G³¯µq¤å¡A½×¤åÃD¥Ø¡G¡u§C¦¨¥» CMOS ´¼¼z«¬·Å«×·P´ú¾¹¤§³]­p»P¹ê§@¡v

u  (102 ¾Ç¦~«×) °ê¥ß°ª¶¯²Ä¤@¬ì§Þ¤j¾Ç¹q¤l¤uµ{¨tºÓ¤h¯Z¡A¾Ç¥Í¡G³¯«a§»¡A½×¤åÃD¥Ø¡G¡u¨ã°¾²¾®É¶¡®ø°£¥\¯à¤§¥þ¼Æ¦ì®É¶¡¦Ü¼Æ¦ìÂà´«¾¹¤§³]­p»P¹ê§@¡v

u  (102 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¹q¾÷¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G§d»Í¯q¡A½×¤åÃD¥Ø¡G¡u¬Û¤Ï¤Î¦P¬Ûª`¤J½¢¦XC¯Å®¶Àú¾¹¤§³]­p»P¤ñ¸û¡v

u  (102 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¹q¾÷¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G³\¥°ª@¡A½×¤åÃD¥Ø¡G¡u§C¥\²v¹q¬y¦A§Q¥Î¤§ÂùÀW±a±µ¦¬¾÷³]­p¡v

u  (102 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê¤u©ÒºÓ¤h¯Z¡A¾Ç¥Í¡GĬ¬f¦t¡A½×¤åÃD¥Ø¡G¡u°w¹ï TI C64x ¼Æ¦ì°T¸¹³B²z¾¹¤§¥iÅܪø«×¶Wªø«ü¥O¦r¤¸½s½X¡v

u  (103 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¹q¾÷¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G¶À¤hªN¡A½×¤åÃD¥Ø¡G¡u³¬°j¸ô¦¡°ª«×¾ã¦XµL½u CMOS ª÷ÄÝÂé½u¥[³t«×­p´¹¤ù³]­p¡v

u  (105 ¾Ç¦~«×) °ê¥ß¥æ³q¤j¾Ç¹q¤l¬ã¨s©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G½²ªø§»¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©óÃþ¯«¸gºô¸ô»P¾÷±ñ¾Ç²ß¤§«]­­«¬ªi¯÷°Ò¼Ò«¬(RBM)³B²z¾¹³]­p¡v

u  (106 ¾Ç¦~«×) °ê¥ß¤¤¤s¤j¾Ç¹q¾÷¬ã¨s©ÒºÓ¤h¯Z¡A¾Ç¥Í¡G¶À¬f¶v¡A½×¤åÃD¥Ø¡G¡u¾A¥Î©ó¤U¤@¥@¥N³q°T¨t²Îªº°ª®Ä¯à·¥©Ê½s½X¾¹¤§³]­p»P¹ê²{¡v

u  (106 ¾Ç¦~«×) »²¤¯¤j¾Ç¹q¾÷¤uµ{¾Ç¨tºÓ¤h¯Z¡A¾Ç¥Í¡G³Å¶®à±¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©ó°ªÀW¶W­µªi¼v¹³¨t²Î¤§¥þ¼Æ¦ì¦Û°Ê¹ïµJµo®gªi§ô¦¨¹³¾¹³]­p¡v

u  (106 ¾Ç¦~«×) »²¤¯¤j¾Ç¹q¾÷¤uµ{¾Ç¨tºÓ¤h¦b¾±M¯Z¡A¾Ç¥Í¡G´¿®aÄQ¡A½×¤åÃD¥Ø¡G¡uÀ³¥Î©ó¨t²Î´¹¤ù¤§§Ö³tÂê©w¥þ¼Æ¦ì©µ¿ðÂê©w°j¸ô¡v

3.      ³Õ¤h¯Z­pµe¤f¸Õ©e­û

u  (97 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G©P®Ñ¥È¡A½×¤åÃD¥Ø¡G¡u§C¥\²v¦h®Ö¤ß´¹¤ù³]­p¤§ÃöÁä¬[ºcÀu¤Æ¡v

u  (97 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G¥j°¶§g¡A½×¤åÃD¥Ø¡G¡u°ª«×¼u©Ê¨t²Î³]­pÀô¹Ò©ó´O¤J¦¡²§½è¦h®Ö¤ß¨t²Î¡v

u  (97 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G±i­×¸Û¡A½×¤åÃD¥Ø¡G¡u§CÀW¼e¥i°ÊºAµe½è¯Á¤Þ¤§ H.264µø°TÀ£ÁY½s½X¾¹¡v

u  (97 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G²°ê¦w¡A½×¤åÃD¥Ø¡G¡uSoftware Optimization of New Generation Video Decoders on Embedded Multi-core Processors¡v

u  (100 ¾Ç¦~«×) °ê¥ß¤¤¥¿¤j¾Ç¸ê°T¤uµ{¬ã¨s©Ò³Õ¤h¯Z¡A¾Ç¥Í¡G²§e¦w¡A½×¤åÃD¥Ø¡G¡uA Remote Real-time Street View Encoding System¡v

4.      ²Ä¤G¤Q©¡¶W¤j«¬¿nÅé¹q¸ô³]­pº[­pºâ¾÷»²§U³]­p§Þ³N¬ã°Q·|(2009 VLSI CAD) Äw³Æ©e­û(¥Í¬¡²Õ¥D®u)»Pijµ{©e­û(Technical Program Committee)

¼Æ¦ì¿nÅé¹q¸ô¤H¤~°ö¨|½Òµ{(Digital IC Training Courses):

1.      ¥þ¼Æ¦ìÂê¬Û°j¸ô³]­p¹ê°È¤ÎÀ³¥Î¹ê¨Ò, ¤u·~§Þ³N¬ã¨s°|²£·~¾Ç°|, ¶}½Ò¤é´Á: 2019/12/07.

2.      ¼Ð·Ç¤¸¥ó®w¿nÅé¹q¸ô³]­p»PÅçÃÒ(Cell-Based IC Physical Design and Verification Lab), ¦Û±j°òª÷·|(TCFST), ¶}½Ò¤é´Á: 2007/04/10.

3.      µwÅé´y­z»y¨¥(Hardware Description Language, Verilog), øʳЬì§Þ(Solid State System), ¶}½Ò¤é´Á: 2007/03/06.

4.      ¼Ð·Ç¤¸¥ó®w¿nÅé¹q¸ô³]­p»PÅçÃÒ(Cell-Based IC Physical Design and Verification Lab), ¦Û±j°òª÷·|(TCFST), ¶}½Ò¤é´Á: 2006/10/24.

5.      ¼Ð·Ç¤¸¥ó®w¿nÅé¹q¸ô³]­p»PÅçÃÒ(Cell-Based IC Physical Design and Verification Lab), ¦Û±j°òª÷·|(TCFST), ¶}½Ò¤é´Á: 2006/04/25.

6.      ¦Û°Ê¤Æ§G§½»PÅçÃÒ¹ê§@½Ò(Auto Placement and Routing Lab), «ä·½¬ì§Þ(SpringSoft), ¶}½Ò¤é´Á: 2006/02/15.

7.      ¶W¤j«¬¿nÅé¹q¸ô³]­p¾É½× (Introduction to VLSI), ¦Û±j°òª÷·|(TCFST), ¶}½Ò¤é´Á: 2005/11/30.

8.      ¼Ð·Ç¤¸¥ó®w¿nÅé¹q¸ô³]­p»PÅçÃÒ(Cell-Based IC Physical Design and Verification Lab), ¦Û±j°òª÷·|(TCFST), ¶}½Ò¤é´Á: 2005/10/18.

9.      §C¥\²v¼Æ¦ì¿nÅé¹q¸ô³]­p(Low-Power Digital IC Design), ¦Û±j°òª÷·|(TCFST), ¶}½Ò¤é´Á: 2005/07/14.

10.  °ò¦¿nÅé¹q¸ô³]­p(Basic VLSI Design), ¤O´¹¥b¾ÉÅé(Powerchip Semiconductor), ¶}½Ò¤é´Á: 2005/07/05.

11.  ¶W¤j«¬¿nÅé¹q¸ô³]­p¾É½×(Introduction to VLSI), ¦Û±j°òª÷·|(TCFST), ¶}½Ò¤é´Á: 2005/03/17.

12.  §C¥\²v¼Æ¦ì¿nÅé¹q¸ô³]­p(Low-Power Digital IC Design), ¦Û±j°òª÷·|(TCFST), ¶}½Ò¤é´Á: 2005/03/04.

13.  §C¥\²v¼Æ¦ì¿nÅé¹q¸ô³]­p(Low-Power Digital IC Design), ¦Û±j°òª÷·|(TCFST), ¶}½Ò¤é´Á: 2004/11/23.

14.  ¼Æ¦ì¿nÅé¹q¸ô¹ê§@½Ò(Digital IC Design Lab), «ä·½¬ì§Þ(SpringSoft), ¶}½Ò¤é´Á: 2004/11/16.

15.  ¼Ð·Ç¤¸¥ó®w¿nÅé¹q¸ô³]­p»PÅçÃÒ(Cell-Based IC Physical Design and Verification Lab), ¥xÆW¥b¾ÉÅé²£·~¨ó·| (TSIA), ¶}½Ò¤é´Á: 2004/08/12.

16.  ¶W¤j«¬¿nÅé¹q¸ô³]­p¾É½×(Introduction to VLSI), ¥æ³q¤j¾Ç¹q¤l¨t¤H¤~°ö°V¤¤¤ß (NCTU NDL), ¶}½Ò¤é´Á: 2004/06/29.

17.  ¶W¤j«¬¿nÅé¹q¸ô³]­p¾É½×(Introduction to VLSI), §»ùÖ´÷±æ IC ³]­p¾Ç°| (Acer Foundation), ¶}½Ò¤é´Á: 2003/09/06.

18.  ¥þ«È¤á¦¡¿nÅé¹q¸ô³]­p»PÅçÃÒ(Full-Custom IC Design Lab), ¥æ³q¤j¾Ç¹q¤l¨t¤H¤~°ö°V¤¤¤ß (NCTU NDL), ¶}½Ò¤é´Á: 2003/07/25.

19.  ¥þ¼Æ¦ìÂê¬Û°j¸ô¤§¿nÅé¹q¸ô³]­p(Design of All-Digital Phase-Locked Loop), ¥æ³q¤j¾Ç¹q¤l¨t¤H¤~°ö°V¤¤¤ß (NCTU NDL), ¶}½Ò¤é´Á: 2003/05/06.

20.  ¥þ«È¤á¦¡¿nÅé¹q¸ô³]­p»PÅçÃÒ(Full-Custom IC Design Lab), ¥æ³q¤j¾Ç¹q¤l¨t¤H¤~°ö°V¤¤¤ß (NCTU NDL), ¶}½Ò¤é´Á: 2002/10/15.

21.  ¥þ¼Æ¦ìÂê¬Û°j¸ô»P¥þ¼Æ¦ì©µ¿ðÂê¬Û°j¸ô³]­p»PÀ³¥Î(Introduction to ADPLL and ADDLL design and its Applications), ¤u¬ã°| (ITRI), ¶}½Ò¤é´Á: 2002/07/31.

22.  ¥þ¼Æ¦ìÂê¬Û°j¸ô¤§¿nÅé¹q¸ô³]­p(Design of All-Digital Phase-Locked Loop), ¥æ³q¤j¾Ç¹q¤l¨t¤H¤~°ö°V¤¤¤ß (NCTU NDL), ¶}½Ò¤é´Á: 2002/07/04.