Ching-Che Chung HomePage

Ching-Che Chung (鍾菁哲) Professor and Chairman
Department of Computer Science and Information Engineering (CSIE) National Chung Cheng University EA406, CSIE Building, No.168, Sec. 1, University Rd., Minhsiung, Chiayi 621301, Taiwan (R.O.C.) TEL: +886-5-272-9395 FAX: +886-5-272-0859 E-mail: wildwolf_AT_cs.ccu.edu.tw 621301嘉義縣民雄鄉大學路一段168號中正大學資工館 406 室 (中正大學地圖) 辦公室直撥電話: (05) 272-9395 (或撥中正總機 (05) 272-0411 轉分機: 33129) 傳真：(05) 272-0859 網頁更新日期： 2024/12/07 ocam: https://www.cs.ccu.edu.tw/~wildwolf/ocam.zip pointer: https://www.cs.ccu.edu.tw/~wildwolf/pointer.zip
中正大學空氣品質即時資訊:
CCU Air Quality
學經歷 (Professional Background):
[2022.08 – 2025.07] 國立中正大學資訊工程學系系主任兼所長兼雲端在職專班主任 [2022.08 – Present ] 臺灣積體電路設計學會(TICD) 理事 [2017.08 – Present ] 國立中正大學資訊工程學系教授 [2012.08 – 2017.07] 國立中正大學資訊工程學系副教授 [2008.08 – 2012.07] 國立中正大學資訊工程學系助理教授 [2008.01 – 2008.07] 國立交通大學晶片系統研究中心博士後研究 [2004.02 – 2009.11] 財團法人鼎天科技教育基金會董事 [2004.01 – 2008.01] 國立交通大學電子研究所系統組博士後研究 [1998.09 – 2003.09] 國立交通大學電子研究所系統組博士 [1993.09 – 1997.08] 國立交通大學電子工程學系學士班
榮譽 (Awards):
1. Most-Read JSSC Articles for 2003 (Recognized by: IEEE, posted Mar 8. 2004.) 2. 2004, “宏碁龍騰論文獎,” 優等 3. 2006, “Low Power Design Contest Award,” at International Symposium on Low Power Electronics and Design (ISLPED) 4. 2011, “Criti-Core 之溫度感知與電源管理電路設計”，國科會整合型計畫「績優計畫獎」 5. 2013, “國立中正大學工學院101學年度青年學者獎” 6. 2015, “國立中正大學工學院103學年度青年學者獎” 7. 2015, “「104 學年度獎勵邁向頂尖大學特殊優秀研究人才暨執行前瞻製造系統頂尖研究中心計畫績優教師彈性薪資案」獎勵金” 8. 2016, “「105 學年度獎勵邁向頂尖大學特殊優秀研究人才暨執行前瞻製造系統頂尖研究中心計畫績優教師彈性薪資案」獎勵金” 9. 2017, “Best Paper Award, second place,” at IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW) 10. 2018, “國立中正大學工學院105學年度優良教學獎” 11. 2018, “國立中正大學107年度教師研究發展獎勵” 12. 2019, “國立中正大學107學年度全校教師優良教學獎” 13. 2019, “國立中正大學108學年度彈性薪資獎勵” 14. 2020, “國立中正大學前瞻製造系統頂尖研究中心 109 學年度「教師獎勵」” 15. 2021, “IEET 中華工程教育協會2021年度教學傑出獎(IEET Distinguished Teaching Award)” 16. 2021, “ViewSonic 創新教師獎 – 複合教學示範競賽優等獎” 17. 2022,“國立中正大學110學年度全校教師優良教學獎” 18. 2023, “國立中正大學前瞻製造系統頂尖研究中心 111 學年度「教師獎勵」”
研究方向 (Research Topics):
1. Artificial intelligence (AI) Chip Design 2. Mixed-Signal IC Design and Sensor Circuits Design 3. Wireless and Wireline Communication Systems 4. Low-Power and System-on-a-Chip (SOC) Design Technology 5. All-digital Phase-Locked Loop/Delay-Locked Loop and Its Applications
矽感測器與系統實驗室 (Silicon Sensor and System Lab, S3Lab):
實驗室成員
資工系開設課程 (Open Courses):
1. 工程數學 (Engineering Mathematics) 開課日期: 2008/09/17, 2009/09/16, 2010/09/15, 2011/9/14, 2016/09/14, 2017/09/20, 2018/09/12, 2019/09/11 2. 數位積體電路設計 (Design of Digital Integrated Circuits and Systems) 開課日期: 2009/02/16, 2010/02/23, 2011/02/22, 2012/02/22, 2013/02/20, 2014/02/19, 2015/02/25, 2016/02/24, 2017/02/22, 2018/03/07, 2019/02/20, 2020/03/04, 2021/02/24, 2022/02/16, 2023/02/15, 2024/02/21 3. 高等數位積體電路設計 (Advanced Digital Integrated Circuits Design) 開課日期：2009/09/15, 2010/09/14, 2011/09/13, 2012/09/18, 2013/09/17, 2014/09/17, 2015/09/15, 2016/09/13, 2017/09/19, 2018/09/11, 2019/09/10, 2020/09/08, 2021/09/14, 2022/09/06, 2023/09/05, 2024/09/10 4. 超大型積體電路設計概論 (Basic VLSI Systems Design) 開課日期：2010/02/22, 2011/02/21, 2012/02/24, 2013/02/22, 2014/02/21, 2015/03/06, 2016/02/26 (全英文授課), 2017/02/24 (全英文授課), 2018/03/02 (全英文授課), 2019/02/22 (全英文授課), 2020/03/06 (全英文授課), 2021/02/26 (全英文授課), 2022/02/18 (全英文授課), 2023/02/17 (全英文授課), 2024/02/23 (全英文授課) 5. 數位電子學 (Electronic Circuits and Electronics) 開課日期：2012/09/17, 2013/09/16, 2014/09/18, 2015/09/16, 2020/09/09, 2021/09/15 (全英文授課), 2022/09/07 (全英文授課), 2023/09/06 (全英文授課), 2024/09/11 (全英文授課)
研究計畫(Projects):
項目		計畫名稱			經費來源	執行期間
1		全自動AI智慧檢傷機器人 [協同主持人]			國科會	2024/11/01 ~ 2025/09/30
2		113 年度先進製程IC 設計及驗證環境建置計畫 [共同主持人]			教育部	2024/07/01 ~ 2025/08/31
3		113年度晶片前瞻技術模組教材發展計畫前瞻運算：邊緣運算人工智慧晶片設計與實作			教育部	2024/01/01 ~ 2025/03/31
4		積體電路設計相關課程的遊戲化教學應用於遠距教學課程 (教學實踐研究計畫)			教育部 PEE1121357	2023/08/01 ~ 2024/07/31
5		111 年度晶片前瞻技術模組教材發展計畫前瞻運算：邊緣運算人工智慧晶片低功率最佳化			教育部	2022/10/01 ~ 2023/09/30
6		強化物聯網終端晶片工作環境監控與建立硬體安全系統之研究(II) (一般型研究計畫)			科技部 MOST 111 - 2221 - E -194 - 049 -	2022/08/01 ~ 2023/07/31
7		強化物聯網終端晶片工作環境監控與建立硬體安全系統之研究 (一般型研究計畫)			科技部 MOST 110 - 2221 - E -194 - 045 -	2021/08/01 ~ 2022/07/31
8		開發深度學習網路硬體加速器應用於工具機故障診斷及預防性維護(I) (一般型研究計畫)			科技部 MOST 108 - 2221 - E -194 - 051 -	2019/08/01 ~ 2020/07/31
9		適用於聲音情境分析之深層類神經網路硬體加速器設計及其應用之節能平台(I) (一般型研究計畫)			科技部 MOST 107 - 2221 - E -194 - 031 -	2018/08/01 ~ 2019/07/31
10		聲音情境分析、應用及其節能電路系統設計--子計畫四：適用於聲音情境分析與應用之節能平台及其深層類神經網路硬體加速器設計 (一般型研究計畫)			科技部 MOST 106 - 2221 - E -194 - 059 -	2017/08/01 ~ 2018/07/31
11		智慧電子整合性人才培育計畫 – 高階應用處理器(AP)相關模組課程發展計畫 - 「晶片時脈責任週期校正電路設計」模組課程計畫(第三年)			教育部	2015/03/01 ~ 2016/04/30
12		1Mbps – 40Mbps 人體通道傳收器設計 (優秀年輕學者研究計畫)			科技部 MOST 103 - 2221 - E -194 - 063 -MY3	2014/08/01 ~ 2017/07/31
13		智慧電子整合性人才培育計畫 – 高階應用處理器(AP)相關模組課程發展計畫 - 「低功率晶片參考時脈電路設計」模組課程計畫 (第二年)			教育部	2014/03/01 ~ 2015/02/28
14		可超寬調壓之智慧視覺處理晶片系統平台 – 子計畫四：針對 UDVS SoC 開發之全數位時脈產生器與晶片匯流排設計 (一般型研究計畫)			國科會 NSC 102 - 2221 - E -194 - 063 -MY3	2013/08/01 ~ 2016/07/31
15		智慧電子整合性人才培育計畫 – 高階應用處理器(AP)相關模組課程發展計畫 - 「低功率時脈產生器」模組課程計畫 (第一年)			教育部	2012/12/01 ~ 2014/02/28
16		針對 A-UDVS iVP SoC 開發之抗變異全數位時脈產生器與晶片匯流排設計 (一般型研究計畫)			國科會 NSC101 - 2221 - E - 194 - 063	2012/08/01 ~ 2013/07/31
17		適用於快閃記憶體系統之錯誤更正編解碼及其硬體架構			建興電子(LiteOn)	2012/06/01 ~ 2014/06/30
18		用於DRAM控制之數位延遲鎖定迴路研究			海思半導體	2011/12/01 ~ 2012/11/30
19		智慧電子整合性人才培育計畫 - 教育部顧問室醫療電子領域 -生醫影像處理系統			教育部	2011/09/01 ~ 2014/01/01
20		低功率儲存系統與高速傳輸界面電路設計 for iF2 Diary) (一般型研究計畫)			國科會 NSC100 - 2221 - E - 194 - 051	2011/08/01 ~ 2012/07/31
21		前瞻晶片系統設計人才培育先導型計畫 – 課程發展計畫 – 教材發展 – 系統晶片驗證平台與實作整合課程			教育部	2010/03/01 ~ 2010/12/31
22		Criti-core: 超越多核心之高可靠度晶片系統平台技術開發 – 子計畫四：Criti-Core 之溫度感知與電源管理電路設計 (國家型科技計畫)			國科會 NSC98 - 2220 - E - 194 - 013 NSC 99 - 2220 - E - 194 - 011	2009/08/01 ~ 2011/07/31
23		前瞻晶片系統設計學程計畫--嵌入式系統軟體學程(ESW)			教育部	2009/03/01 ~ 2011/01/31
24		快速相位鎖定高頻率倍數全數位鎖相迴路設計與應用之研究 (新進人員研究計畫)			國科會 NSC 97 - 2218 - E - 194 - 009 - MY2	2008/11/01 ~ 2010/07/31
25		使用只需金屬層便可重新程式化的標準元件庫開發全數位多相位時脈產生器及全數位鎖相迴路用於0.13um CMOS製程的SoC產品開發(Develop All-Digital Multi-Phase Clock Generator and All-Digital Phase-Locked Loop on Metal Programmable Cell Array (MPCA) for SoC products on 0.13um CMOS Process)			智原科技(Faraday)	2005/01/01 ~ 2005/12/31
已發表著作的被引用情形(My Citations)
Google Scholar (Author: Ching-Che Chung) Scopus Data (Scopus ID: 57762571600) ScholarGPS (ID: 76716711735352) [Ranking Analytics]
已發表著作 (期刊 Journal Papers):
// Impact Factor (IF): 2023 JCR Science Edition (https://www.isiknowledge.com/JCR) // H-index: 20 (by Google Scholar) (https://en.wikipedia.org/wiki/H-index) // SCI Citation Count (https://www.isiknowledge.com) // Google Citation Count (https://scholar.google.com.tw/) 1. Yu-Pei Liang, Hao Chen (學生), and Ching-Che Chung, “A one-dimensional depthwise separable convolutional neural network for bearing fault diagnosis implemented on FPGA,” Sensors, vol. 24, no. 23, Art no. 7831, Dec. 2024. [pdf] [SCI, EI, IF=3.4, Rank=122/352 (34.7%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST111-2221-E-194-049)* 2. Yu-Pei Liang, Chen-Ming Chang (學生), and Ching-Che Chung, “Implementation of lightweight convolutional neural networks with an early exit mechanism utilizing 40 nm CMOS process for fire detection in unmanned aerial vehicles,” Sensors, vol. 24, no. 7, Art no. 2265, Apr. 2024. [pdf] [SCI, EI, IF=3.4, Rank=122/352 (34.7%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST111-2221-E-194-049)* 3. Yu-Pei Liang, Yao-Shun Hsu (學生), and Ching-Che Chung, “A low-power hierarchical CNN hardware accelerator for bearing fault diagnosis,” IEEE Transactions on Instrumentation and Measurement, vol. 73, Art no. 3508511, Jan. 2024. [pdf] [SCI, EI, IF=5.6, Rank=9/76 (11.8%) in Instruments and Instrumentation, Rank=53/352 (15.1%) in Engineering, Electrical Electronics,* SCI Cited: 0, Google Cited: 0] (MOST111-2221-E-194-049) 4. Yu-Pei Liang, Ming-You Hung (學生), and Ching-Che Chung, “A multiplier-free convolution neural network hardware accelerator for real-time bearing condition detection of CNC machinery,” Sensors, vol. 23, no. 23, Art no. 9437, Nov. 2023. [pdf] [SCI, EI, IF=3.4, Rank=122/352 (34.7%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST111-2221-E-194-049)* 5. Ching-Che Chung, Yu-Pei Liang, and Hong-Jin Jiang (學生), “CNN hardware accelerator for real-time bearing fault diagnosis,” Sensors, vol. 23, no. 13, Art no. 5897, Jun. 2023. [pdf] [SCI, EI, IF=3.4, Rank=122/352 (34.7%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST111-2221-E-194-049)* 6. Tsung-Hsien Liu, Ting-Xu Jiang (學生), Ching-Che Chung, and Yuan-Sun Chu, “A maximum logarithmic maximum a posteriori probability based soft-input soft-output detector for the coded spatial modulation systems,” IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 69, no. 9, pp. 3816-3828, Sep. 2022. [pdf] [SCI, EI, IF=5.1, Rank=68/275 (24.7%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST109-2221-E-194-032-MY2)* 7. Ching-Che Chung, Duo Sheng, and Ming-Hsuan Li (學生), “Design of a Human Body Channel Communication Transceiver Using Convolutional Codes,” Microelectronics Journal, vol. 100, Art no. 104783, Jun. 2020. [pdf] [SCI, EI, IF=1.405, Rank=192/266 (72.2%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST108-2221-E-194-051) 8. Ching-Che Chung, Duo Sheng, Ming-Chieh Li (學生), and Yi-Che Tsai (學生), “A fast phase tracking reference-less all-digital CDR circuit for human body channel communication,” Microelectronics Journal, vol. 84, pp. 87-95, Feb. 2019. [pdf] [SCI, EI, IF=1.405, Rank=192/266 (72.2%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST107-2221-E-194-031) 9. Ching-Che Chung* and Chi-Yu Hou (學生), “An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications,” Microelectronics Journal, vol. 70, pp. 63-71, Dec. 2017. [pdf] [SCI, EI, IF=1.322, Rank=175/260 (67.3%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST103-2221-E- 194-063-MY3) 10. Ching-Che Chung* and Chien-Ying Yu (學生), “An area-efficient and wide-range digital DLL for per-pin deskew applications,” Turkish Journal of Electrical Engineering and Computer Sciences, vol. 25, no. 3, pp. 2185-2194, May 2017. [pdf] [SCI, EI, IF=0.580, Rank=231/260 (88.8%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST103-2221-E- 194-063-MY3) 11. Ching-Che Chung* and Jhih-Wei Li (學生), “A cell-based 5-MHz on-chip clock generator,” Turkish Journal of Electrical Engineering and Computer Sciences, vol. 25, no. 2, pp. 1472-1482, Apr. 2017. [pdf] [SCI, EI, IF=0.580, Rank=231/260 (88.8%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC102-2221-E-194- 063-MY3) 12. Ching-Che Chung* and Chi-Kuang Lo (學生), “A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology, “ IEICE Electronics Express (ELEX), vol. 13, no. 17, 20160749, Aug. 2016. [pdf] [SCI, EI, IF=0.456, Rank=245/262 (93.5%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (MOST103-2221-E- 194-063-MY3) 13. Ching-Che Chung, Wei-Siang Su(學生), and Chi-Kuang Lo(學生), “A 0.52V/1.0V fast lock-in ADPLL for supporting dynamic voltage and frequency scaling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1, pp. 408-412, Jan. 2016. [pdf] [SCI, EI, IF=1.698, Rank=21/52 (40.4%)* in Computer Science, Hardware & Architecture, Rank=127/262 (48.5%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC102-2221-E-194-063-MY3) 14. Ching-Che Chung, Duo Sheng, and Chang-Jun Li(學生), “A wide-range low-cost all-digital duty-cycle corrector,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2487-2496, Nov. 2015. [pdf] [SCI, EI, IF=1.245, Rank=19/51 (37.3%)* in Computer Science, Hardware & Architecture, Rank=132/257 (51.4%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC102-2221-E-194-063-MY3) 15. Ching-Che Chung, Duo Sheng, and Wei-Da Ho(學生), “A low-cost low-power all-digital spread-spectrum clock generator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 983-987, May 2015. [pdf] [SCI, EI, IF=1.245, Rank=19/51 (37.3%)* in Computer Science, Hardware & Architecture, Rank=132/257 (51.4%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC102-2221-E-194-063-MY3) 16. Ching-Che Chung* and Hao-Hsiang Hsu(學生), “Partial parity cache and data cache management method to improve the performance of an SSD-based RAID,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 7, pp. 1470-1480, Jul. 2014. [pdf] [SCI, EI, IF=1.356, Rank=16/50 (32.0%) in Computer Science, Hardware & Architecture, Rank=111/249 (44.6%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC100-2221-E-194-051) 17. Ching-Che Chung, Duo Sheng, and Sung-En Shen(學生), “High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1096-1105, May 2014. [pdf] [SCI, EI, IF=1.356, Rank=16/50 (32.0%)* in Computer Science, Hardware & Architecture, Rank=111/249 (44.6%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC101-2221-E-194-063) 18. Duo Sheng, Ching-Che Chung, Hsiu-Fan Lai(學生), and Shu-Syun Jhao(學生), “High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications, “ IEICE Electronics Express (ELEX)* , vol. 11, no. 3, 20131011, Jan. 2014. [pdf] [SCI, EI, IF=0.391, Rank=211/248 (85.1%) in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC101-2221-E-030-025) 19. Ching-Che Chung, Duo Sheng, and Wei-Da Ho(學生), “A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS, “ IEICE Electronics Express (ELEX), vol. 10, no. 6, 20130090, Mar. 2013. [pdf] [SCI, EI, IF=0.391, Rank=211/248 (85.1%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC101-2221-E-194-063) 20. Ching-Che Chung, Duo Sheng, and Ning-Mi Hsueh(學生), “A high-performance wear-leveling algorithm for flash memory system, “ IEICE Electronics Express (ELEX), vol. 9, no. 24, pp. 1874-1880, Dec. 2012. [pdf] [SCI, EI, IF=0.268, Rank=223/243 (91.7%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 1] (NSC100-2221-E-194-051) 21. Wei-Hao Sung(學生), Ming-Che Lee(學生), Ching-Che Chung, and Chen-Yi Lee, “An ultra-low voltage implicit multiplexed differential flip-flop with enhanced noise immunity,” Electronics Letters, vol. 48, no. 23, pp. 1452-1454, Nov. 2012. [pdf] [SCI, EI, IF=1.038, Rank=128/243 (52.6%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC100-2220-E-009-016) 22. Chien-Ying Yu(學生), Ching-Che Chung, Chia-Jung Yu(學生), and Chen-Yi Lee, “A low-power DCO using interlaced hysteresis delay cells, “ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 10, pp. 673-677, Oct. 2012. [pdf] [SCI, EI, IF=1.327, Rank=96/243 (39.5%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC100-2220-E-009-016) 23. Ching-Che Chung, Duo Sheng, Chia-Lin Chang(學生), Wei-Da Ho(學生), Yang-Di Lin(學生), and Fang-Nien Lu(學生), “An all-digital large-N audio frequency synthesizer for HDMI applications, “ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 7, pp. 424-428, Jul. 2012. [pdf] [SCI, EI, IF=1.327, Rank=96/243 (39.5%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC100-2221-E-194-051) 24. Duo Sheng, Ching-Che Chung, Jhih-Ci Lan(學生), and Hsiou-Fan Lai(學生), “Monotonic and low-power digitally controlled oscillator with portability for SoC applications,” Electronics Letters, vol. 48, no. 6, pp. 321-323, Mar. 2012. [pdf] [SCI, EI, IF=1.038, Rank=128/243 (52.6%)* in Engineering, Electrical Electronics, SCI Cited: 1, Google Cited: 0] (NSC100-2221-E-030-012) 25. Ching-Che Chung* and Chiun-Yao Ko(學生), “A fast phase tracking ADPLL for video pixel clock generation in 65 nm CMOS technology, “ IEEE Journal of Solid-State Circuits, vol. 46, no. 10, pp. 2300-2311, Oct. 2011. [pdf] [SCI, EI, IF=3.226, Rank=15/245 (6.1%) in Engineering, Electrical Electronics, SCI Cited: 3, Google Cited: 16] (NSC97-2218-E-194-009-MY2) 26. Ching-Che Chung, Duo Sheng, and Sung-En Shen(學生), “A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65 nm CMOS technology, “ IEICE Electronics Express (ELEX)* , vol. 8, no. 15, pp. 1245-1251, Aug. 2011. [pdf] [SCI, EI, IF=0.461, Rank=195/245 (79.6%) in Engineering, Electrical Electronics, SCI Cited: 2, Google Cited: 1] (NSC99-2220-E-194-011) 27. Ching-Che Chung, Jui-Yuan Yu(學生), Shiou-Ru Jang(學生), and Chen-Yi Lee, “A 90 nm all-digital smart temperature sensor with wireless body area network baseband transceiver for biotelemetry applications,” Journal of Signal Processing Systems for Signal Image and Video Technology, vol. 46, no. 2, pp. 241-248, Aug. 2011. [pdf] [SCI, EI, IF=0.672, Rank=165/245 (67.3%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC99-2220-E-194-011) 28. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “A low-power and portable spread spectrum clock generator for SoC applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 6, pp. 1113-1117, Jun. 2011. [pdf] [SCI, EI, IF=1.219, Rank=15/50 (30.0%)* in Computer Science, Hardware & Architecture, Rank=105/245 (42.8%) in Engineering, Electrical Electronics, SCI Cited: 4, Google Cited: 7] (NSC96-2221-E-009-181) 29. Ching-Che Chung, Duo Sheng, and Chia-Lin Chang(學生), “A 600 kHz to 1.2 GHz all-digital delay-locked loop in 65 nm CMOS technology,” IEICE Electronics Express (ELEX), vol. 8, no. 7, pp. 518-524, Apr. 2011. [pdf] [SCI, EI, IF=0.461, Rank=195/245 (79.6%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC97-2218-E-194-009-MY2) 30. Ching-Che Chung, Chiun-Yao Ko(學生), and Sung-En Shen(學生), “Built-in self-calibration circuit for monotonic digitally controlled oscillator design in 65-nm CMOS technology, “ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 3, pp. 149-153, Mar. 2011. [pdf]. [SCI, EI, IF=1.410, Rank=88/245 (35.9%)* in Engineering, Electrical Electronics, SCI Cited: 3, Google Cited: 4] (NSC97-2218-E-194-009-MY2) 31. Ching-Che Chung* and Cheng-Ruei Yang(學生), “An autocalibrated all-digital temperature sensor for on-chip thermal monitoring, “ IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 2, pp. 105-109, Feb. 2011. [pdf] [SCI, EI, IF=1.410, Rank=88/245 (35.9%) in Engineering, Electrical Electronics, SCI Cited: 7, Google Cited: 28] (NSC99-2220-E-194-011) 32. Duo Sheng(學生), Ching-Che Chung, and Chen-Yi Lee, “Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications,” IEICE Electronics Express (ELEX), vol. 7, no. 9, pp. 634-639, May 2010. [pdf] [SCI, EI, IF=0.427, Rank=195/247 (78.9%)* in Engineering, Electrical Electronics, SCI Cited: 2, Google Cited: 4] (NSC96-2221-E-009-181) 33. Duo Sheng(學生), Ching-Che Chung, and Chen-Yi Lee, “Wide duty cycle range synchronous mirror delay designs,” Electronics Letters, vol. 46, no. 5, pp. 338-340, Mar. 2010. [pdf] [SCI, EI, IF=1.004, Rank=124/247 (50.2%)* in Engineering, Electrical Electronics, SCI Cited: 0, Google Cited: 0] (NSC96-2221-E-009-181) 34. Jui-Yuan Yu(學生), Ching-Che Chung, and Chen-Yi Lee, “A symbol-rate timing synchronization method for low power wireless OFDM systems,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 9, pp. 922-926, Sep. 2008. [pdf] [SCI, EI, IF=1.436, Rank=78/229 (34.1%)* in Engineering, Electrical Electronics, SCI Cited: 3, Google Cited: 7] (MOEA 95-EC-17-A-03-S1-0005) 35. Duo Sheng(學生), Ching-Che Chung, and Chen-Yi Lee, “An ultra-low-power and portable digitally controlled oscillator for SoC applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 11, pp. 954-958, Nov. 2007. [pdf] [SCI, EI, IF=1.104, Rank=76/227 (33.5%)* in Engineering, Electrical Electronics, SCI Cited: 18, Google Cited: 48] (NSC95-2220-E-009-291) 36. Pao-Lung Chen(學生), Ching-Che Chung, Jyh-Neng Yang, and Chen-Yi Lee, “A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications,” IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1275-1285, Jun. 2006. [pdf] [SCI, EI, IF=2.002, Rank=25/206 (12.1%)* in Engineering, Electrical Electronics, SCI Cited: 24, Google Cited: 44] (NSC93-2220-E-009-033) 37. Pao-Lung Chen(學生), Ching-Che Chung, and Chen-Yi Lee, “A portable digitally controlled oscillator using novel varactors,” IEEE Transaction on Circuits and System II: Analog and Digital Signal Processing, vol. 52, no. 5, pp. 233-237, May 2005. [pdf] [SCI, EI, IF=0.661, Rank=110/208 (52.9%)* in Engineering, Electrical Electronics, SCI Cited: 32, Google Cited: 75] (NSC93-2220-E-009-033) 38. Pao-Lung Chen(學生), Ching-Che Chung, and Chen-Yi Lee, “A novel digitally-controlled varactor for portable delay cell design,” IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E87-A, no .12, pp. 3324-3326, Dec. 2004. [pdf] [SCI, EI, IF=0.318, Rank=154/209 (73.7%)* in Engineering, Electrical Electronics, SCI Cited: 4, Google Cited: 2] (NSC92-2220-E-009-019) 39. Ching-Che Chung and Chen-Yi Lee, “A new DLL-based approach for all-digital multiphase clock generation,” IEEE Journal of Solid-State Circuits, vol. 39, no. 3, pp. 469-475, Mar. 2004. [pdf] [SCI, EI, IF=1.756, Rank=29/209 (13.9%)* in Engineering, Electrical Electronics, SCI Cited: 32, Google Cited: 61] (NSC90-2215-E-009-105) 40. Ching-Che Chung and Chen-Yi Lee, “An all-digital phase-locked loop for high-speed clock generation,” IEEE Journal of Solid-State Circuits, vol.38, no. 2, pp. 347-351, Feb. 2003. [pdf] [SCI, EI, IF=2.035, Rank=22/205 (10.7%)* in Engineering, Electrical Electronics, SCI Cited: 73, Google Cited: 160] (NSC90-2215-E-009-105)
已發表著作 (重要國際會議 Top Conferences):
1. Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao and Chen-Yi Lee, “A sub-mW multi-tone CDMA baseband transceiver chipset for wireless body area network applications, “ in Digest of Technical Papers, IEEE Solid-State Circuits Conference (ISSCC), Feb. 2007, pp. 364-365. [pdf] [EI, Google Cited: 8] (MOEA 95-EC-17-A-03-S1-0005) 2. Tsu-Ming Liu, Ching-Che Chung, Ting-An Lin, Sheng-Zen Wang, and Chen-Yi Lee, “Design of a 125mW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications, “ in Proceedings of 43rd ACM/IEEE Design Automation Conference (DAC), Jul. 2006, pp. 288-289. [pdf] [EI, Google Cited: 7] (NSC94-2215-E-009-046) 3. Summary: Not available.Jui-Yuan Yu, Ching-Che Chung, Hsuan-Yu Liu, Yu-Wei Lin, Wan-Chun Liao, Terng-Yin Hsu, and Chen-Yi Lee, “A 31.2mW UWB baseband transceiver with all-digital I/Q-mismatch calibration and dynamic sampling, “ in Digest of Technical Papers, Symposium on VLSI Circuits, Jun. 2006, pp. 236-237. [pdf] [EI, Google Cited: 10] (MOEA 95-EC-17-A-03-S1-0005) 4. Hsuan-Yu Liu, Chien-Ching Lin, Yu-Wei Lin, Ching-Che Chung, Kai-Li Lin, Wei-Che Chang, Lin-Hung Chen, Hsie-Chia Chang, and Chen-Yi Lee, “A 480Mb/s LDPC-COFDM-based UWB baseband transceiver, “ in Digest of Technical Papers, IEEE Solid-State Circuits Conference (ISSCC), Feb. 2005, pp.444-446. [pdf] [EI, Google Cited: 37] (MOEA 95-EC-17-A-03-S1-0005) 5. Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Ching Lin, Ching-Che Chung, Terng-Yi Hsu, and Chen-Yi Lee, “A COFDM baseband processor with robust synchronization for high-speed WLAN applications, “ in Digest of Technical Papers, Symposium on VLSI Circuits, Jun. 2004, pp. 156-159. [pdf] [EI] (MOEA 95-EC-17-A-03-S1-0005)
已發表著作 (會議論文 Conference Papers):
1. Yu-Pei Liang, Hui-Hsuan Chang, and Ching-Che Chung, “A low-power convolutional neural network implemented in 40-nm CMOS technology for bearing fault diagnosis,” in Proceedings of International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Apr. 2024. [pdf] [EI] (MOST111- 2221-E-194-049-) 2. Ching-Che Chung, Yu-Pei Liang, and Jo-Chen Huang, “Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery,” in Proceedings of IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW), Jul. 2023, pp. 133-134. [pdf] [EI] (MOST111- 2221-E-194-049-) 3. Ching-Che Chung, Yu-Pei Liang, Ya-Ching Chang, and Chen-Ming Chang, “A binary weight convolutional neural network hardware accelerator for analysis faults of the CNC machinery on FPGA,” in Proceedings of International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Apr. 2023. [pdf] [EI] (MOST111- 2221-E-194-049-) 4. Ching-Che Chung and Yi-Ting Tsai, “A body channel communication transceiver with a 16x oversampling CDR and convolutional codes,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2022. [pdf] [EI] (MOST110-2221-E-194-045-) 5. Ching-Che Chung, Huai-Xiang Zhang, Ming-You Hung, and Hong-Jin Jian, “A DBN hardware accelerator for auditory scene classification,” in Proceedings of IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW), Sep. 2020. [pdf] [EI] (MOST108-2221-E-194-051) 6. Ching-Che Chung, Wei-Ting Chen, and Ya-Ching Chang, “Using Quantization-Aware Training Technique with Post-Training Fine-Tuning Quantization to Implement a MobileNet Hardware Accelerator,” in Proceedings of 2020 Indo-Taiwan 2nd International Conference on Computing, Analytics and Networks (Indo-Taiwan ICAN), Feb. 2020, pp. 28-32. [pdf] [EI] (MOST108-2221-E-194-051) 7. Ching-Che Chung and Hsin-Han Huang, “An all-digital temperature sensor with process and voltage variation tolerance for IoT applications,” in Proceedings of 32nd IEEE International System-on-Chip Conference (SOCC), Sep. 2019, pp. 109-112. [pdf] [EI] (MOST108-2221-E-194-051) 8. Ching-Che Chung, Wei-Jung Chu, and Yi-Ting Tsai, “Built-in Self-Test Circuits for All-digital Phase-Locked Loops,” in Proceedings of IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW), May. 2019. [pdf] [EI] (MOST107-2221-E- 194-031) 9. Ching-Che Chung, Yi-Zeng Lee, and Huai-Xiang Zhang, “Design of a DBN hardware accelerator for handwritten digit recognitions,” in Proceedings of IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW), May. 2019. [pdf] [EI] (MOST107-2221-E-194-031) 10. Ching-Che Chung, Wei-Jung Chu, and Yi-Ting Tsai, “An all-digital built-in self-test circuit for ADPLLs in 65nm CMOS technology,” in Proceedings of 29th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2018. [pdf] (MOST106-2221-E-194-059) 11. Ching-Che Chung, Ru-Hua Chang, and Ming-Hsuan Li, “An FPGA-based transceiver for human body channel communication using Walsh Codes,” in Proceedings of IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW), May. 2018. [pdf] [EI] (MOST106-2221-E-194-059) 12. Ching-Che Chung, Dai-Hua Lee, and Yu-Hsin Wang, “FPGA-based accelerator platform for K-means clustering algorithm,” in Proceedings of Annual Conference on Engineering and Applied Science (ACEAT), Nov. 2017, pp. 41-50. [pdf] (MOST106-2221-E-194-059) 13. Ching-Che Chung and Yu-Hsin Wang, “Hadoop cluster with FPGA-based hardware accelerators for K-means clustering algorithm,” in Proceedings of IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW), Jun. 2017, pp. 143-144. [pdf] [EI] (MOST103- 2221-E-194-063-MY3) (Best Paper Award, Second Place) 14. Ching-Che Chung, Yi-Che Tsai, and Ming-Chieh Li, “A reference-less all-digital transceiver for human body channel communication,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2017. [pdf] [EI] (MOST103- 2221-E-194-063-MY3) 15. Ching-Che Chung, Chih-Yu Lin, and Jia-Zong Yang, “Time-domain characteristics of body channel communication (BCC) and BCC transceiver design,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2016. [pdf] [EI] (MOST103- 2221-E-194-063-MY3) 16. Ching-Che Chung and Mei-I Sun, “An all-digital voltage sensor for static voltage drop measurements,” in Proceedings of IEEE Sensors Applications Symposium (SAS), Apr. 2016. [pdf] [EI] (MOST103- 2221-E-194-063-MY3) 17. Ching-Che Chung, Mei-I Sun, and Yi-Che Tsai, “An all-digital on-chip voltage sensor for SoC design,” in Proceedings of 26th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2015. [pdf] (NSC102- 2221-E-194-063-MY3) 18. Duo Sheng, Ching-Che Chung, Chia-Lin Wu, Sheng-Min Chan, and Min-Rong Hong, “An all-digital and wide-range reference clock generator for biotelemetry applications,” in Proceedings of International Conference on Electronics and Software Science (ICESS), Jul. 2015, pp. 118-123. [pdf] (MOST103- 2221-E-030-025) 19. Ching-Che Chung, Chen-Han Chen, and Chi-Kuang Lo, “A DCO compiler for all-digital PLL design,” in Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Jun. 2015, pp. 543-546. [pdf] [EI] (NSC102- 2221-E-194-063-MY3) 20. Ching-Che Chung, Chun-Kai Liu, and Dai-Hua Lee, “FPGA-based accelerator platform for Big data matrix processing,” in Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Jun. 2015, pp. 221-224. [pdf] [EI] (NSC102- 2221-E-194-063-MY3) 21. Ching-Che Chung, Chi-Tung Chang, and Chih-Yu Lin, “A 1 Mb/s – 40Mb/s human body channel communication transceiver,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2015. [pdf] [EI] (MOST103- 2221-E-194-063-MY3) 22. Ching-Che Chung and Jhih-Wei Li, “An all-digital on-chip abnormal temperature warning sensor for dynamic thermal management,” in Proceedings of 27th IEEE International System-on-Chip Conference (SOCC), Sep. 2014, pp. 221-224. [pdf] [EI] (NSC102- 2221-E-194-063-MY3) 23. Ching-Che Chung, Chi-Tung Chang, Chuan-Yi Wu, Yu-Te Liao, and Chih-Yu Lin, “A 1 Mb/s – 40 Mb/s human body channel communication transceiver,” in Proceedings of 25th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2014. [pdf] (NSC102- 2221-E-194-063-MY3) 24. Ching-Che Chung, Duo Sheng, and Chen-Han Chen, “An all-digital phase-locked loop compiler with liberty timing files,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2014. [pdf] [EI] (NSC102- 2221-E-194-063-MY3) 25. Ching-Che Chung and Chi-Yu Hou, “All-digital delay-locked loop for 3D-IC die-to-die clock synchronization,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2014. [pdf] [EI] (NSC102- 2221-E-194-063-MY3) 26. Ching-Che Chung, Shu-Xian Shen, Chuan-Yi Wu, Yu-Te Liao, and Chi-Tung Chang, “A 1 Mb/s – 40 Mb/s WBS transceiver for human body channel communication,” in Proceedings of 24th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2013. [pdf] (NSC101-2221-E-194-063) 27. Duo Sheng, Ching-Che Chung, Chih-Chung Huang, and Jia-Wei Jian, “A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications,” in Proceedings of 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Jul. 2013, pp. 2461-2464. [pdf] [EI] (NSC101-2221-E-030-025) 28. Ching-Che Chung and Jhih-Wei Li, “An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2013, pp. 2682-2685. [pdf] [EI] (NSC101-2221-E-194-063) 29. Ching-Che Chung, Duo Sheng, and Wei-Siang Su, “A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2013. [pdf] [EI] (NSC101-2221-E-194-063) 30. Ching-Che Chung and Chang-Jun Li, “A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2013. [pdf] [EI] (NSC101-2221-E-194-063) 31. Ching-Che Chung and Ning-Mi Hsueh, “A low-complexity high-performance wear-leveling algorithm for flash memory system design,” in Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2012, pp. 595-598. [pdf] [EI] (NSC100-2221-E-194-051) 32. Ching-Che Chung, Duo Sheng, and Yang-Di Lin, “An all-digital clock and data recovery circuit for spread spectrum clocking applications in 65nm CMOS technology,” in Proceedings of International Asia Symposium on Quality Electronic Design (ASQED), Jul. 2012, pp. 91-94. [pdf] [EI] (NSC100-2221-E-194-051) 33. Duo Sheng, Ching-Che Chung, and Jhih-Ci Lan, “A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications,” in Proceedings of International Asia Symposium on Quality Electronic Design (ASQED), Jul. 2012, pp. 123-127. [pdf] [EI] (NSC100-2221-E-030-012) 34. Ching-Che Chung, Duo Sheng, and Wei-Da Ho, “A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2012. [pdf] [EI] (NSC100-2221-E-194-051) 35. Ching-Che Chung, Sung-En Shen and Wei-Da Ho, “A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology,” in Proceedings of 22th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2011, pp. 380-383. [pdf] (NSC99-2220-E-194-011) 36. Ching-Che Chung and Wei-Cheng Dai, “A referenceless all-digital fast frequency acquisition full-rate CDR circuit for USB 2.0 in 65nm CMOS technology,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2011, pp. 217-220. [pdf] [EI] (NSC99-2220-E-194-011) 37. Ching-Che Chung and Wei-Jung Chu, “An all-digital on-chip jitter measurement circuit in 65nm CMOS technology,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2011, pp. 179-182. [pdf] [EI] (NSC99-2220-E-194-011) 38. Ching-Che Chung, Chiun-Yao Ko and Sung-En Shen, “A monotonic digitally controlled oscillator with self-calibration in 65nm CMOS technology,” in Proceedings of 21th VLSI Design/CAD Symposium (VLSI CAD), Aug. 2010, pp. 327-330. [pdf] (NSC97-2218-E-194-009-MY2) 39. Ching-Che Chung and Cheng-Ruei Yang, “An all-digital smart temperature sensor with auto-calibration in 65nm CMOS technology,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2010, pp. 4089-4092. [pdf] [EI] (NSC98-2220-E-194-013) 40. Ching-Che Chung and Chia-Lin Chang, “A wide-range all-digital delay-locked loop in 65nm CMOS technology,” in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2010, pp. 66-69. [pdf] [EI] (NSC97-2218-E-194-009-MY2) 41. Chia-Chi Hsiao, Hung-Ming Chen and Ching-Che Chung, “Yield improvement in memory compiler generated SRAM with inter-die variations,” in Proceedings of 15th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2009), Mar. 2009, pp. 450-455. [pdf] (NSC97-2220-E-009-004) 42. Duo Sheng, Ching-Che Chung and Chen-Yi Lee, “An all digital spread spectrum clock generator with programmable spread ratio for SoC applications, “ in Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2008, pp. 850-853. [pdf] [EI] (NSC96-2221-E-009-181) 43. Jui-Yuan Yu, Juinn-Ting Chen, Mei-Hui Yang, Ching-Che Chung, and Chen-Yi Lee, “An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems, “ in Proceedings of 2007 IEEE International SOC Conference, Sep. 2007, pp. 305-308. [pdf] [EI] (MOEA 95-EC-17-A-03-S1-0005) 44. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “A fast-lock-in ADPLL with high-resolution and low-power DCO for SoC applications, “ in Proceedings of 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2006, pp. 105-108. [pdf] [EI] (NSC95-2220-E-009-291) 45. Jui-Yuan Yu, Ching-Che Chung, Hsuan-Yu Liu, and Chen-Yi Lee, “Power reduction with dynamic sampling and all-digital I/Q-mismatch calibration for a MB-OFDM UWB baseband transceiver, “ in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), Oct. 2006. [pdf] (MOEA 95-EC-17-A-03-S1-0005) 46. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “An all-digital phase-locked loop with high resolution for SoC applications, “ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2006, pp. 207-210. [pdf] [EI] (NSC95-2220-E-009-291) 47. Ching-Che Chung, Pao-Lung Chen, and Chen-Yi Lee, “An all-digital delay-locked Loop for DDR SDRAM controller applications, “ in Proceedings of International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2006, pp. 199-202. [pdf] [EI] (NSC93-2220-E-009-033) 48. Pao-Lung Chen, Ching-Che Chung and Chen-Yi Lee, “An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications, “ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 4875-4878. [pdf] [EI]Summary: Not available..... (NSC93-2220-E-009-033) 49. Hsie-Chia Chang, Ching-Che Chung, Chien-Ching Lin, and Chen-Yi Lee, “A 300 MHz Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm, “ in Proceedings of European Solid-State Circuits Conf. (ESSCIRC), Sep. 2002, pp. 519-522. [pdf] (NSC90-2218-E-009-035) 50. Ching-Che Chung and Chen-Yi Lee, “An all-digital phase-locked loop for high-speed clock generation, “ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2002, pp.26-29. [pdf] [EI] (NSC90-2215-E-009-105) 51. Ching-Che Chung and Chen-Yi Lee, “A novel structure for portable digitally controlled oscillator, “ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2001, pp.272-275. [pdf] [EI] (NSC90-2215-E-009-105) 52. Yew-San Lee, Ching-Che Chung, Tsyr-Shiou Perng, Li-Chyun Hsu, Ming-Yang Jaw, and Chen-Yi Lee, “A memory-based architecture for very high throughput variable length codec design, “ in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Jun. 1997, pp. 9-12. [pdf] [EI] (NSC86-2221-E-009-016)
已發表著作 (Ph.D. Dissertation):
博士論文：應用於系統晶片設計之自動化合成時序鎖相迴路 Automatic Synthesis of Timing-Locked Loops for SoC Designs [pdf]
專利(Patents):
1. Ching-Che Chung and Wei-Da Ho(學生), “All-digital spread spectrum clock generating circuit with EMI reduction effect and a method for controlling the same, “ US patent 9,450,641 B2, Sep. 2016. 2. 鍾菁哲, 何威達(學生), “具電磁干擾效應衰減之全數位展頻時脈產生電路及其控制方法, “ 中華民國專利第 I505642號, 民國104年. 3. 鍾菁哲, 沈頌恩(學生), “全數位時脈校正電路及其方法, “ 中華民國專利第 I448081 號, 民國103年 08 月 01 日. 4. Ching-Che Chung and Sung-En Shen(學生), “Full-digital Clock Correction Circuit and Method Thereof, “ US patent 8,487,680 B1, Jul. 16, 2013. 5. 李鎮宜, 鍾菁哲, “用於全數位鎖相迴路設計之數位濾波器, “ 中華民國專利第 I360950 號, 民國101年03月21日. 6. Chen-Yi Lee and Ching-Che Chung, “ Digital Loop Filter for All-Digital Phase-Locked Loop Design, “ US patent 7,696,832 B1, Apr.13, 2010.
演講記錄(Speeches):
1. “介紹零信任資安(Zero Trust)的硬體安全技術 PUF (Physically Unclonable Function)”, 私立亞洲大學資電學院專題講座, 2022/12/08 2. “人體通道傳收器”, 國立嘉義大學電機系, 2021/03/03 3. “人體通道傳收器”, 私立輔仁大學電機系, 2020/06/17 4. “全數位鎖相迴路技術及其應用介紹”, 國立中山大學電機系, 2016/10/04 5. “全數位鎖相迴路技術及其應用介紹”, 國立高雄第一科技大學電通系, 2016/03/24 6. “資工系學生的硬體設計能力培養”,國立屏東大學資工系, 2015/10/05 7. “All-Digital High-Speed Clock Generator and Thermal Sensor for Supporting DVFS in a Ultra-low-Power Processor”, 高階應用處理器AP聯盟 2014 系統晶片設計國際研習課程,國立交通大學, 2014/08/13 8. “數位電路能拿來作什麼?”, 國立高雄第一科技大學電子系, 2013/03/14 9. “數位電路能拿來作什麼?”, 私立輔仁大學電機系, 2011/11/02 10. “All-Digital PLL Design”,國立雲林科技大學電機系, 2010/04/09. 11. “Low-Power SoC Physical Design”,國立中正大學資工系, 2008/03/07. 12. “Low-Power SoC Design”,國立成功大學電機系, 2007/09/27. 13. “All-Digital PLL/DLL Design and Its Applications”,國立交通大學電信系, 2007/05/24. 14. “All-Digital PLL Design”, 親民技術學院電子系, 2005/05/04.
S3 LAB學生畢業論文(S3 LAB Dissertations) :
項目	學年度		姓名	論文題目
1	98		柯鈞耀	快速相位追蹤與高頻率倍數全數位鎖相迴路設計與應用 Fast Phase Tracking and High Frequency Multiplication Factor All-Digital Phase-Locked Loop and Its Applications. [pdf]
2	98		張嘉麟	適用寬頻操作之全數位延遲鎖相迴路 A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS technology. [pdf]
3	98		楊承叡	全數位自動校正智慧型溫度偵測晶片 All-Digital Smart Temperature Sensor with Self-Calibration in 65nm CMOS Technology. [pdf]
4	99		戴偉丞	可應用於 USB 2.0 之無參考時脈全數位快速鎖定之連續速率資料與時脈回復電路 An Referenceless All-Digital Fast Frequency Acquisition Full-Rate Continuous Rate CDR Circuit for USB 2.0 in 65nm CMOS Technology. [pdf]
5	99		朱薇蓉	應用於全數位鎖相迴路之自我測試電路設計 Design of All-Digital Built-In Self-Test Circuit for All-Digital Phase-Locked Loops. [pdf]
6	99		沈頌恩	應用於寬頻操作之全數位時脈責任週期校正與輸出相位對齊電路 A Wide-Range All-Digital Duty-Cycle Corrector with Output Clock Phase Alignment in 65nm CMOS Technology. [pdf]
7	99		張家銘	應用於動態系統效能調整之嵌入式溫度與電路延遲感測器與系統驗證技術開發 On-Chip Temperature and Delay Sensors for Adaptive System Design and System Verification with SVA. [pdf]
8	100		薛甯謐	可應用於快閃記憶體系統設計之高效能及低複雜度平面化演算法 A Low-Complexity High-Performance Wear-Leveling Algorithm for Flash Memory System Design. [pdf]
9	100		林揚迪	應用於展頻序列通訊之全數位資料回復電路 An All-Digital Clock and Data Recovery Circuit for Spread Spectrum SerDes Applications. [pdf]
10	100		許皓翔	可應用於改善固態硬碟磁碟陣列之存取效能的同位元檢查碼及資料的快取管理機制 A Parity Check and Data Cache Management Method to Improve the Performance of a Solid-State Disk-Based RAID. [pdf]
11	100		何威達	具有極佳的電磁干擾效應衰減效果之全數位展頻時脈產生器 Design of All-Digital Spread-Spectrum Clock Generator with High EMI Reduction. [pdf]
12	101		李誌偉	使用標準邏輯元件設計並可補償製程電壓及溫度變異對輸出頻率影響之嵌入式矽振盪器 A cell-based on-chip silicon oscillator for frequency compensation with PVT variations. [pdf]
13	101		李長潤	可工作於 0.5V/1.0V並具有非對稱製程飄移容忍度之低功耗延遲線重複利用全數位責任週期校正電路 A 0.5V/1.0V low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance. [pdf]
14	101		蘇煒翔	可支援動態電壓與頻率調整之快速鎖定 0.5V/1.0V 全數位鎖相迴路設計 A 0.5V/1.0V fast lock-in ADPLL for supporting dynamic voltage and frequency scaling. [pdf]
15	101		沈書賢	1Mbps – 40Mbps 人體通道傳收器設計 Design of 1 Mbps – 40 Mbps human body channel communication transceiver. [pdf]
16	102		陳貞翰	開發奈米製程下之全數位鎖相迴路自動產生器 Develop an all-digital phase-locked loop compiler in nanometer CMOS technologies. [pdf]
17	102		張棋棟	1Mbps– 40Mbps 人體通道傳收器設計與實現 Design and Implementation of a 1 Mbps – 40 Mbps human body channel communication transceiver. [pdf]
18	102		侯紀宇	應用於三維晶片時脈同步之全數位延遲鎖相迴路 An all-digital delay-locked loop for 3D ICs die-to-die clock synchronization. [pdf]
19	102		劉俊凱	開發與實現可應用於巨量資料分析之FPGA 硬體加速平台 Development and Implementation of an FPGA-based hardware accelerator for big data analysis. [pdf]
20	103		林致佑	人體通道傳輸特性與設計人體通道傳收器 Characteristics of the human body channel and design the human body channel transceiver. [pdf]
21	103		李岱樺	用於資料密集型運算之高擴展性FPGA 硬體加速平台 High Scalability FPGA-based hardware accelerator for data-intensive computation. [pdf]
22	103		羅啟光	40 奈米製程下開發與設計快速鎖定之全數位鎖相迴路 Design of A Fast Lock-In All-Digital Phase-Locked Loop in 40-nm CMOS technology. [pdf]
23	103		孫美怡	使用標準邏輯元件及相對式參考模型技術設計之靜態電壓壓降偵測器與嵌入式矽振盪器 Design of a static IR-drop monitor and an on-chip silicon oscillator with cell-based and relative reference modelling approaches. [pdf]
24	104		蔡宜哲	可應用於人體通道傳輸之無參考時脈全數位資料與回復電路設計 A Reference-Less All-Digital CDR Circuit for Human Body Channel Communication. [pdf]
25	104		王宥芯	建構於可程式化邏輯板實現硬體加速之Hadoop 叢集用於資料探勘演算法 Hadoop Cluster with FPGA-based Hardware Accelerators for Data Mining Algorithms. [pdf]
26	104		楊佳榮	建構於可程式邏輯板之人體通道傳輸收發器設計 An FPGA-based Transceiver for Human Body Channel Communication Applications. [pdf]
27	105		李銘傑	可應用於人體通道傳輸且具有快速相位追蹤功能的無參考時脈全數位資料與回復電路設計 Fast Phase Tracking Reference-Less All-Digital CDR Circuit for Human Body Channel Communication. [pdf]
28	105		張茹華	使用華氏碼並建構於可程式邏輯板之人體通道傳輸收發器 An FPGA-based Transceiver for Human Body Channel Communication using Walsh Codes. [pdf]
29	106		李奕增	用於手寫數字辨識的DBN硬體加速器設計 Design of a DBN hardware accelerator for handwritten digit recognition. [pdf]
30	106		黃信翰	一個適用於物聯網應用並可抵抗製程與電壓變異的全數位溫度感測器 An All-digital Temperature Sensor with Process and Voltage Variations Tolerance for IoT Applications. [pdf]
31	106		李銘軒	使用卷積碼並建構於可程式邏輯板之人體通道傳輸收發器之設計與實現 Design and Implementation of a Human Body Channel Communication Transceiver on FPGA Using Convolutional Codes. [pdf]
32	107		洪國展	K-means 演算法硬體加速器的設計和實現 Design and implementation of a hardware accelerator for K-means algorithm. [pdf]
33	107		張淮翔	使用K-means 演算法用於訓練後量化來實現用於聽覺場景分類的DNN硬體加速器 A DNN Hardware Accelerator for Auditory Scene Classification Using the K-means Clustering Algorithm in Post-Training Quantization. [pdf]
34	107		蔡宜庭	使用十六倍超取樣時脈與資料回復電路及卷積碼的人體通道傳輸收發器 A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes. [pdf]
35	107		陳威廷	使用量化感知訓練技術搭配訓練後微調量化來實現 MobileNet 硬體加速器 Using Quantization-Aware Training Technique with Post-Training Fine-Tuning Quantization to Implement a MobileNet Hardware Accelerator. [pdf]
36	108		黃若榛	使用三元量化方法實現之輕量級卷積神經網路硬體加速器用於CNC工具機即時故障診斷 Lightweight Convolutional Neural Network Hardware Accelerator Using the Ternary Quantization Method for Real-Time Fault Diagnosis of CNC Machinery. [pdf]
37	108		楊閔琁	使用遞迴方法抵抗製程、電壓與溫度變異的集成式電壓與溫度感測器 Integrated Voltage and Temperature Sensors that Use Recursive Methods to Resist Process, Voltage, and Temperature Variations. [pdf]
38	108		張雅晴	使用FPGA實現之二元化卷積神經網路硬體加速器應用於 CNC 工具機故障分析 A Binary Weight Convolutional Neural Network Hardware Accelerator for Analysis Faults of the CNC Machinery on FPGA. [pdf]
39	108		洪銘佑	用於CNC 工具機即時軸承狀態檢測之無乘法器卷積神經網路硬體加速器 A multiplier-free convolution neural network hardware accelerator for real-time bearing condition detection of CNC machinery. [pdf]
40	109		陳逸帆	使用漏電流元件建立的集成式電壓與溫度感測器並能抵抗製程、電壓與溫度變異 Integrated voltage and temperature sensors built with leakage current components and resistant to process, voltage and temperature variations. [pdf]
41	109		簡宏晉	基於電流訊號的軸承故障診斷使用一維卷積神經網路並於FPGA實現 A one-dimensional convolutional neural network implemented on FPGA for bearing fault diagnosis based on the current signals. [pdf]
42	109		張慧萱	通過分析電流訊號進行軸承故障診斷之低功耗卷積神經網路使用40 奈米製程實現 A low-power convolutional neural network implemented in 40-nm CMOS technology for bearing fault diagnosis by analyzing current signals. [pdf]
43	109		彭詩涵	開發可有效抵抗機器學習的物理不可複製函數和全數位鎖相迴路的同步時鐘域研究 Development of a Physical Unclonable Function (PUF) that can effectively resist machine learning and an ADPLL clock domain synchronization research. [pdf]
44	110		洪佳偉	使用自我校正的數位控制振盪器用於集成式電壓與溫度感測器並能抵抗製程、電壓與溫度變異 Use self-calibrating digitally controlled oscillators for integrated voltage and temperature sensors and are resistant to the process, voltage, and temperature variations. [pdf]
45	110		陳品樺	卷積神經網路硬體加速器的快速設計流程研究並於FPGA實現 Research on the rapid design process of a hardware accelerator for convolutional neural networks and its implementation on FPGA. [pdf]
46	110		溫俊諺	開發高可靠度且對機器學習攻擊具有強大抵抗力的物理不可複製函數(PUF) Develop highly reliable physically unclonable functions (PUFs) with robust resistance to machine learning attacks. [pdf]
47	110		陳顥	在FPGA上實現用於軸承故障診斷的一維深度可分離卷積神經網絡 A one-dimensional depthwise separable convolutional neural network for bearing fault diagnosis implemented on FPGA. [pdf]
48	110		許堯舜	採用 40 奈米製程實現之用於軸承故障診斷的低功耗分層卷積神經網路硬體加速器 A low-power hierarchical convolutional neural network hardware accelerator implemented in 40-nm CMOS technology for bearing fault diagnosis. [pdf]
49	110		詹上熠	應用於深度信念網路的S型函數之高效率硬體實現 Efficient hardware implementation of Sigmoid function in deep belief networks. [pdf]
50	111		鐘晨心	開發與設計實現針對聯邦式學習之卷積神經網路訓練的硬體加速器 Development and Design of a Hardware Accelerator for Convolutional Neural Network Training in Federated Learning. [pdf]
51	111		王湘綾	設計與優化使用40nm CMOS製程實現的快速鎖定全數位鎖相迴路 Design and Optimization of Fast-Lock All-Digital Phase-Locked Loop Implemented using 40nm CMOS Process. [pdf]
52	111		黃韋翔	基於隱藏挑戰回應配對機制並對機械學習展現強化抵抗力的物理不可複製函數開發 Development of Physically Unclonable Functions (PUFs) Based on Hidden Challenge-Response Pair Mechanisms with Enhanced Resistance to Machine Learning. [pdf]
53	111		張宸銘	利用40奈米製程實現帶有提前退出機制的輕量級卷積神經網路於無人飛行載具火災偵測之應用 Implementation of Lightweight Convolutional Neural Networks with Early Exit Mechanism Utilizing 40nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles. [pdf]
54	111		黃紹軒	設計與實現40奈米CMOS製程的PAM-4接收器與等化器研究 Development and Implementation of PAM-4 Receiver and Equalizer Using 40-nm CMOS Process. [pdf]
55	112		江怡均	40nm CMOS 技術下使用加強 DCO 線性度設計實現的快速鎖定全數位鎖相迴路 Implementation of a Fast-Locking All-Digital PLL with an Enhanced Linearity DCO in 40nm CMOS Technology. [pdf]
56	112		晁文勤	使用16奈米CMOS技術及提前退出機制實現之低功耗分支卷積神經網路硬體加速器用於無人機災害檢測 Low-Power Branch CNN Hardware Accelerator with Early Exit for UAV Disaster Detection Using 16nm CMOS Technology. [pdf]
57	112		許成誼	採用16奈米技術實現之用於即時表情識別應用的低功耗階層式卷積神經網路硬體加速器 Low-Power Hierarchical CNN Hardware Accelerator Using 16nm Technology for Real-Time Facial Expression Recognition Applications. [pdf]
58	112		黃韋銘	基於16nm CMOS技術的高效能混合專家卷積神經網路於無人機災害檢測之應用 An Energy-Efficient Convolutional Neural Network with Mixture-of-Experts for UAV-Based Disaster Detection in 16nm CMOS Technology. [pdf]
59	112		林芮蝶	基於物理不可複製函數的安全認證協議設計及秘密回應反饋機制 Design of a Security Authentication Protocol Based on Physical Unclonable Functions (PUFs) with a Secret Response Feedback Mechanism. [pdf]
服務(Services) :
系委員(資訊工程學系) 1. 擔任大學部事務小組委員 a. 協助大學部甄試招生事宜 b. 協助規劃大學部課程規劃 c. 協助規劃學士班新生修業規定 d. 擔任班導師 2. 擔任研究所事務小組委員 3. 擔任系務發展委員會委員 a. 協助進行 IEET 工程及科技教育認證 b. 協助進行課程檢討與核心能力統計 4. 擔任經費設備小組委員 a. 協助創新大樓新增空間規劃 b. 系上空間使用分配規劃 c. 系上經費使用分配規劃 d. 系上 501 教學實驗室SUN/Linux 工作站管理與維護 e. 系上 206 電腦教室經費與採購項目規劃 5. 擔任課程委員會委員 6. 擔任招生委員會委員 7. 擔任學士班甄選入學審查及口試委員 8. 擔任碩士班甄試審查及口試委員 9. 擔任碩士班招生命題及閱卷委員 10. 擔任博士班招生審查及口試委員 11. 擔任博士班甄試審查及口試委員 12. 擔任博士班資格考命題委員校委員 1. 擔任教學意見調查委員會委員工學院代表其他服務事蹟 1. 論文審查委員 a. 期刊 u IEEE Journal of Solid-State Circuits (JSSC) u IEEE Transactions on Circuits and Systems I&II (TCAS-I, II) u IEEE Transactions on VLSI Systems (TVLSI) u IEEE Signal Processing Letters (SPL) u Journal of VLSI Signal Processing u International Journal of Electrical Engineering (IJEE) b. 研討會 u Technical Program Committee (TPC) for IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT 2012 - 2018) u Technical Program Committee (TPC) for IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004) u University Design Contest Committee for Asia and South Pacific Design Automation Conference (ASP-DAC 2010) u Session Chair for IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT 2010 - 2014) u Session Chair (PLL/DLL) for 2010 VLSI Design/CAD Symposium u IEEE Solid-State Circuits Conference (ISSCC) u IEEE Asian Solid-State Circuits Conference (A-SSCC) u IEEE Symposium on Circuits and Systems (ISCAS) u IEEE International Conference on Electronics, Circuits, and Systems (ICECS) u Design, Automation & Test in Europe (DATE) 2. 碩博士學位口試委員 u (96 學年度) 國立交通大學電子所碩士班，學生：張琇茹，論文題目：「應用於視訊系統之快速相位追蹤與高頻率倍數全數位式鎖相迴路」 u (96 學年度) 國立交通大學電子所碩士班，學生：陳俊廷，論文題目：「應用於無線近身網路之可調式全數位時脈產生器」 u (96 學年度) 國立交通大學電子所碩士班，學生：黃上賓，論文題目：「應用於無線近身網路之嵌入式晶體震盪器」 u (97 學年度) 國立交通大學電子所碩士班，學生：賴昱帆，論文題目：「應用於 SVC 視訊編碼標準之空間可適應性內幀解碼器設計」 u (97 學年度) 國立交通大學電子所碩士班，學生：馬曉涵，論文題目：「應用於正交分頻多工技術為基礎之無石英無線進身網路同步器」 u (97 學年度) 國立交通大學電機學院 IC 設計產業研發碩士班，學生：楊智超，論文題目：「嵌入式晶體震盪器之時脈產生器設計」 u (97 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：劉俊甫，論文題目：「多相位數位鎖相迴路電路設計」 u (97 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：林琮翔，論文題目：「數位控制多相位延遲鎖定迴路使用改良型校準技術」 u (98 學年度) 國立中正大學資訊工程研究所碩士班，學生：蘇亮妃，論文題目：「採用共同表格分割策略之多模式熵編解碼器」 u (98 學年度) 國立中正大學資訊工程研究所碩士班，學生：梁益詮，論文題目：「應用於高畫質電視之H.264/AVS雙重模式動態補償系統設計」 u (98 學年度) 國立中正大學資訊工程研究所碩士班，學生：許嫣蘭，論文題目：「基於測試存取機制之非集中式除錯架構內多核心除錯輔助處理器」 u (98 學年度) 國立中正大學資訊工程研究所碩士班，學生：鄭軒博，論文題目：「以 FPGA 實現無一致性快取記憶體基於環形架構晶片網路多核心系統」 u (98 學年度) 國立中正大學資訊工程研究所碩士班，學生：郭士齊，論文題目：「利用時間解碼器及時間偷取技術之可調性多週期處理器」 u (98 學年度) 國立中正大學資訊工程研究所碩士班，學生：蔡長宏，論文題目：「應用於 H.264/SVC/Multi-View 視訊編碼之可支援動態搜尋範圍移動預測矽智財設計」 u (98 學年度) 國立中正大學資訊工程研究所碩士班，學生：楊致全，論文題目：「具動態模式選擇之分數型移動估測矽智財設計」 u (98 學年度) 國立中正大學資訊工程研究所碩士班，學生：張道城，論文題目：「應用於嵌入式平台下之低複雜度影片暨影像接合演算法」 u (98 學年度) 國立中正大學資訊工程研究所碩士班，學生：李馨怡，論文題目：「平行化可調式 H.264 解碼器架構設計」 u (99 學年度) 交通大學電機學院微電子奈米科技產業研發碩士班，學生：郭時明，論文題目：「以時間轉換數位為基礎之低成本溫度感測器設計」 u (99 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：王子祥，論文題目：「多相位自我校準之重覆逼近暫存器延遲鎖定迴路」 u (99 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：邱俊翰，論文題目：「多相位具有監控計數之全數位鎖相迴路」 u (99 學年度) 國立中正大學資訊工程研究所博士班，學生：周書玄，論文題目：「低功率多核心晶片設計之關鍵架構優化」 u (100 學年度) 國立中正大學電機工程研究所博士班，學生：葉長青，論文題目：「利用預先喚醒式電源閘控策略於處理器功能單元以達到低功率計算並維持效能之研究」 u (100 學年度) 國立交通大學電子與光電學程碩士班，學生：游佳融，論文題目：「具有交錯型遲滯延遲元件的低功耗數位控制震盪器」 u (101 學年度) 國立交通大學電子所博士班，學生：宋偉豪，論文題目：「應用於無線近身網路之低耗能基頻處理器設計」 u (101 學年度) 國立中正大學資訊工程研究所博士班，學生：簡國安，論文題目：「應用於立體視訊執行緒管線平行之驗證感知設計方法」 u (101 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：陳廷曜，論文題目：「LFSR 具隨機儲存裝置之研究」 u (101 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：林三祥，論文題目：「全數位鎖相迴路運用 LFSR 及飛加器之研究」 u (101 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：鄭奇欣，論文題目：「虛擬隨機存儲架構結合飛加器頻率合成器之實現與分析」 u (101 學年度) 國立高雄第一科技大學電子工程系碩士班，學生：劉耿志，論文題目：「基於脈衝縮減與脈衝擴增之高解析度互補式金氧半時間至數位轉換器」 u (101 學年度) 國立高雄第一科技大學電子工程系碩士班，學生：林世豪，論文題目：「具曲率校正及單點校正支援之全數位智慧型溫度感測器之設計與實作」 u (102 學年度) 國立中正大學電機研究所碩士班，學生：吳銓益，論文題目：「反相及同相注入耦合 C級振盪器之設計與比較」 u (102 學年度) 國立中正大學電機研究所碩士班，學生：許弘昇，論文題目：「低功率電流共利用之雙頻帶接收機設計」 u (102 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：李偉嘉，論文題目：「全數位鎖相迴路具動態頻率計數之研究」 u (102 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：李大成，論文題目：「虛擬隨機存儲應用之研究」 u (102 學年度) 國立高雄第一科技大學電腦與通訊工程所碩士班，學生：吳承洪，論文題目：「飛加器與 LFSR 隨機存儲裝置之研究」 u (102 學年度) 國立高雄第一科技大學電子工程系碩士班，學生：陳皓文，論文題目：「低成本 CMOS 智慧型溫度感測器之設計與實作」 u (102 學年度) 國立高雄第一科技大學電子工程系碩士班，學生：陳冠宏，論文題目：「具偏移時間消除功能之全數位時間至數位轉換器之設計與實作」 u (102 學年度) 國立中正大學電機研究所碩士班，學生：吳銓益，論文題目：「相反及同相注入耦合C級振盪器之設計與比較」 u (102 學年度) 國立中正大學電機研究所碩士班，學生：許弘昇，論文題目：「低功率電流再利用之雙頻帶接收機設計」 u (102 學年度) 國立中正大學資工所碩士班，學生：蘇柏宇，論文題目：「針對 TI C64x 數位訊號處理器之可變長度超長指令字元編碼」 u (103 學年度) 國立中正大學電機研究所碩士班，學生：黃士杰，論文題目：「閉迴路式高度整合無線 CMOS 金屬鎊線加速度計晶片設計」 u (105 學年度) 國立交通大學電子研究所博士班，學生：蔡長宏，論文題目：「應用於類神經網路與機械學習之侷限型波茲曼模型(RBM)處理器設計」 u (106 學年度) 國立中山大學電機研究所碩士班，學生：黃柏鈞，論文題目：「適用於下一世代通訊系統的高效能極性編碼器之設計與實現」 u (106 學年度) 輔仁大學電機工程學系碩士班，學生：傅雅鈺，論文題目：「應用於高頻超音波影像系統之全數位自動對焦發射波束成像器設計」 u (106 學年度) 輔仁大學電機工程學系碩士在職專班，學生：曾家麒，論文題目：「應用於系統晶片之快速鎖定全數位延遲鎖定迴路」 3. 博士班計畫口試委員 u (97 學年度) 國立中正大學資訊工程研究所博士班，學生：周書玄，論文題目：「低功率多核心晶片設計之關鍵架構優化」 u (97 學年度) 國立中正大學資訊工程研究所博士班，學生：古偉君，論文題目：「高度彈性系統設計環境於嵌入式異質多核心系統」 u (97 學年度) 國立中正大學資訊工程研究所博士班，學生：張修誠，論文題目：「低頻寬可動態畫質索引之 H.264視訊壓縮編碼器」 u (97 學年度) 國立中正大學資訊工程研究所博士班，學生：簡國安，論文題目：「Software Optimization of New Generation Video Decoders on Embedded Multi-core Processors」 u (100 學年度) 國立中正大學資訊工程研究所博士班，學生：簡呈安，論文題目：「A Remote Real-time Street View Encoding System」 4. 第二十屆超大型積體電路設計暨計算機輔助設計技術研討會(2009 VLSI CAD) 籌備委員(生活組主席)與議程委員(Technical Program Committee)
數位積體電路人才培育課程(Digital IC Training Courses):
1. 全數位鎖相迴路設計實務及應用實例, 工業技術研究院產業學院, 開課日期: 2019/12/07. 2. 標準元件庫積體電路設計與驗證(Cell-Based IC Physical Design and Verification Lab), 自強基金會(TCFST), 開課日期: 2007/04/10. 3. 硬體描述語言(Hardware Description Language, Verilog), 鑫創科技(Solid State System), 開課日期: 2007/03/06. 4. 標準元件庫積體電路設計與驗證(Cell-Based IC Physical Design and Verification Lab), 自強基金會(TCFST), 開課日期: 2006/10/24. 5. 標準元件庫積體電路設計與驗證(Cell-Based IC Physical Design and Verification Lab), 自強基金會(TCFST), 開課日期: 2006/04/25. 6. 自動化佈局與驗證實作課(Auto Placement and Routing Lab), 思源科技(SpringSoft), 開課日期: 2006/02/15. 7. 超大型積體電路設計導論 (Introduction to VLSI), 自強基金會(TCFST), 開課日期: 2005/11/30. 8. 標準元件庫積體電路設計與驗證(Cell-Based IC Physical Design and Verification Lab), 自強基金會(TCFST), 開課日期: 2005/10/18. 9. 低功率數位積體電路設計(Low-Power Digital IC Design), 自強基金會(TCFST), 開課日期: 2005/07/14. 10. 基礎積體電路設計(Basic VLSI Design), 力晶半導體(Powerchip Semiconductor), 開課日期: 2005/07/05. 11. 超大型積體電路設計導論(Introduction to VLSI), 自強基金會(TCFST), 開課日期: 2005/03/17. 12. 低功率數位積體電路設計(Low-Power Digital IC Design), 自強基金會(TCFST), 開課日期: 2005/03/04. 13. 低功率數位積體電路設計(Low-Power Digital IC Design), 自強基金會(TCFST), 開課日期: 2004/11/23. 14. 數位積體電路實作課(Digital IC Design Lab), 思源科技(SpringSoft), 開課日期: 2004/11/16. 15. 標準元件庫積體電路設計與驗證(Cell-Based IC Physical Design and Verification Lab), 台灣半導體產業協會 (TSIA), 開課日期: 2004/08/12. 16. 超大型積體電路設計導論(Introduction to VLSI), 交通大學電子系人才培訓中心 (NCTU NDL), 開課日期: 2004/06/29. 17. 超大型積體電路設計導論(Introduction to VLSI), 宏碁渴望 IC 設計學院 (Acer Foundation), 開課日期: 2003/09/06. 18. 全客戶式積體電路設計與驗證(Full-Custom IC Design Lab), 交通大學電子系人才培訓中心 (NCTU NDL), 開課日期: 2003/07/25. 19. 全數位鎖相迴路之積體電路設計(Design of All-Digital Phase-Locked Loop), 交通大學電子系人才培訓中心 (NCTU NDL), 開課日期: 2003/05/06. 20. 全客戶式積體電路設計與驗證(Full-Custom IC Design Lab), 交通大學電子系人才培訓中心 (NCTU NDL), 開課日期: 2002/10/15. 21. 全數位鎖相迴路與全數位延遲鎖相迴路設計與應用(Introduction to ADPLL and ADDLL design and its Applications), 工研院 (ITRI), 開課日期: 2002/07/31. 22. 全數位鎖相迴路之積體電路設計(Design of All-Digital Phase-Locked Loop), 交通大學電子系人才培訓中心 (NCTU NDL), 開課日期: 2002/07/04.