Publications

Journal Papers

  1. Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, and Tien-Fu Chen, "Zero-counting and adaptive-latency cache using a voltage-guardband breakthrough for energy-efficient operations," IEEE Transactions on Circuits and Systems - II: Express Briefs, vol. 63, Oct. 2016 (SCI, EI)
  2. Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, and Tien-Fu Chen, "Cross-matching caches: dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors," Integration, the VLSI Journal, vol. 54, Jun. 2016 (SCI, EI)
  3. Tay-Jyi Lin and Ting-Yu Shyu, "Speculative lookahead for energy-efficient microprocessors," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, Jan. 2016 (SCI & EI)
  4. Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-Wen Hsueh, and Naehyuck Chang, "System-level performance and power optimization for MPSoC - A memory access-aware approach," ACM Transactions on Embedded Computing, vol. 14, Jan. 2015 (SCI & EI)
  5. Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, and Yen-Hsiang Yu, "A 4R/2W register file design for UDVS microprocessors in 65nm CMOS," IEEE Transactions on Circuits and Systems - II: Express Briefs, vol. 59, Dec. 2012 (SCI, EI)
  6. Yu-Ting Kuo, Tay-Jyi Lin, and Chih-Wei Liu, "Complexity-aware quantization and lightweight VLSI implementation of FIR filters," EURASIP Journal on Advances in Signal Processing, vol. 2011, 2011 (SCI, EI)
  7. Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, and Tay-Jyi Lin, "Hierarchical circuit-switched NoC for multicore video processing," Microprocessors and Microsystems, vol. 35, Mar. 2011 (SCI, EI)
  8. Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq-Kuen Lee, Yuan-Hua Chu, and An-Yeu Wu, "Parallel architecture core (PAC) - the first multicore application processor SoC in Taiwan: Part I hardware architecture & software development tools," Journal of Signal Processing Systems, vol. 62, Mar. 2011 (SCI, EI)
  9. Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, and Chih-Wei Liu, "Design & implementation of low-power ANSI S1.11 filter bank for digital hearing aids," IEEE Transactions on Circuits and Systems - I: Regular Papers, vol. 57, July 2010 (SCI, EI)
  10. Tay-Jyi Lin, Pi-Chen Hsiao, Shin-Kai Chen, Yu-Ting Kuo, and Chih-Wei Liu, "Design & implementation of a high-performance & complexity-effective VLIW DSP for multimedia applications," Journal of Signal Processing Systems, vol. 51, Jun. 2008 [pdf] (SCI, EI)
  11. Tay-Jyi Lin, Pi-Chen Hsiao, Chih-Wei Liu, and Chein-Wei Jen, "Area-efficient register organization for fully-synthesizable VLIW DSP cores," International Journal of Electrical Engineering, vol. 13, May 2006 (EI)
  12. Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, and Chein-Wei Jen, "A compact DSP core with static floating-point arithmetic," Journal of VLSI Signal Processing, vol. 42, Feb. 2006 [pdf] (SCI, EI)

Conference Papers

    International

  1. Chiao-Chuan Huang, Hsin Yang, Ting-Yu Shyu, and Tay-Jyi Lin, "Timing margin prediction for energy-efficient and variation-resilient adaptive voltage scaling in microprocessor designs," accepted and to appear in VMC, Austin, Nov. 2016
  2. Pei-Yuan Chou, Wei-Ling Lin, Tay-Jyi Lin, Jyh-Herng Wang, and Jinn-Shyang Wang, "A low-power low-cost built-in jitter measurement circuit for DDR4-2133," accepted and to appear in ICSICT, Hangzhou, Oct. 2016
  3. Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, and Jinn-Shyan Wang, "Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation," in Proc. SOCC, Seattle, Sep. 2016
  4. Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Tien-Fu Chen, and Jinn-Shyan Wang, "Variable-length VLIW encoding for code size reduction in embedded processors," in Proc. SOCC, Seattle, Sep. 2016
  5. Bo-Hao Chen, Pei-Yuan Chou, Ya-Bei Fang, Lee-Kee Yong, Tay-Jyi Lin, and Jinn-Shyan Wang, "Design of ultra-low-leakage near-threshold dynamic circuits in nano CMOS for IoT applications," in Proc. NANO, Sendai, Aug. 2016
  6. Chi-Hsuan Kao, Zih-Hong Yang, Cheng-Lan Huang, Yu-Sian Chang, Chung-Wei Wu, Ting-Yu Shyu, Pei-Yuan Chou, Tay-Jyi Lin, and Jinn-Shyan Wang, "Characterization of delay variations in modern FPGAs," in Proc. VMC, Austin, Nov. 2015
  7. Pei-Yuan Chou, I-Chen Wu, Jia-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, and Jinn-Shyan Wang, "Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches," in Proc. ASICON, Chengdu, Nov. 2015
  8. Pei-Yuan Chou, Chung-Ling Liou, Jinn-Shyan Wang, and Tay-Jyi Lin, "Operation-condition and timing-error collaborative monitoring for fixed-latency AVS designs," in Proc. ICSICT, Guilin, Oct. 2014
  9. Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsun Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, and Jinn-Shyan Wang, "Low-power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET)," in Proc. Hot Chips, Cupertino, Aug. 2014
  10. Bo-Yuan Yang, Cheng-Chun Chang, and Tay-Jyi Lin, "Respiratory rhythm extraction for driver's drowsiness assessment," in Proc. ARIS, Taipei, Jun. 2014
  11. Chingwei Yeh, Cheng-Yao Tsai, Tay-Jyi Lin, and Jiun-In Guo, "Maintaining color fidelity for dual-shot HDR imaging," in Proc. ICCE-TW, Taipei, May 2014
  12. Yung-Hui Yu, Po-Hao Wang, Tien-Fu Chen, Tay-Jyi Lin, and Jinn-Shyan Wang, "Adaptive variable-latency cache management for low-voltage caches," in Proc. FTFC, Monaco, May 2014
  13. Bo-Yuan Yang, Cheng-Chun Chang, Yi-Hsuan Ting, Jia-Wei Liao, Hong-Li Lin, Tay-Jyi Lin, Chingwei Yeh, and Jinn-Shyan Wang, "Accelerometer-based breathing signal acquisition with empirical mode decomposition," in Proc. ICISA, Seoul, May 2014
  14. Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, and Tien-Fu Chen, "Variation-aware and adaptive-latency accesses for reliable low voltage caches," in Proc. VLSI-SoC, Istanbul, Oct. 2013
  15. Jinn-Shyan Wang, Keng-Jui Chang, Tay-Jyi Lin, Richard Wu Prasojo, and Chingwei Yeh, "A 0.36V, 33.3uW 18-band ANSI S1.11 1/3-octave filter bank for digital hearing aids in 40nm CMOS," in Proc. VLSI Circuits, Kyoto, Jun. 2013
  16. Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C.H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, and Jinn-Shyan Wang, "A 0.48V 0.57nJ/pixel video recording SoC in 65nm CMOS," in Proc. ISSCC, San Francisco, Feb. 2013
  17. Shih-Hao Ou, Che-Wei Yeh, Tay-Jyi Lin, and Chih-Wei Liu, "A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor," in Proc. ISCAS, Seoul, May 2012
  18. Tay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, and Yuan-Hua Chu, "Energy-efficient RISC design with on-demand circuit-level timing speculation," in Proc. ASP-DAC, Sydney, Jan. 2012
  19. Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, and Chingwei Yeh, "Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications," in Proc. ASP-DAC, Sydney, Jan. 2012
  20. Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, and Naehyuck Chang, "Hierarchical memory scheduling for multimedia MPSoCs," in Proc. ICCAD, San Jose, Nov. 2010
  21. Kuo-Chiang Chang, Yu-Ting Kuo, Tay-Jyi Lin, and Chih-Wei Liu, "Complexity-effective dynamic range compression for digital hearing aids," in Proc. ISCAS, Paris, May 2010
  22. Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, and Chih-Wei Liu, "Improving energy efficiency of functional units by exploiting their data-dependent latency," in Proc. ISCAS, Paris, May 2010
  23. Tay-Jyi Lin, Pi-Cheng Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, and Yuan-Hua Chu, "Collaborative voltage scaling with online STA and variable-latency datapath," in Proc. GLSVLSI, Providence, May 2010
  24. Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, and Tay-Jyi Lin, "RunAssert: a non-intrusive run-time assertion for parallel programs debugging," in Proc. DATE, Dresden, Mar. 2010
  25. Pi-Cheng Hsiao, Chi-Hung Lin, Kuo-Cheng Lee, and Tay-Jyi Lin, "Fast design space exploration for MPSoC architectures," in Proc. ICCES, Cairo, Dec. 2009
  26. Chi-Hung Lin, Pi-Cheng Hsiao, Ching-Hsiang Chuang, and Tay-Jyi Lin, "Fast architecture exploration with hierarchical trace simulations," in Proc. ISOCC, Busan, Nov. 2009
  27. Ching-Hsiang Chuang, Chiu-Ling Chen, Pi-Cheng Hsiao, and Tay-Jyi Lin, "Software development tools for streaming DSP applications," in Proc. ISOCC, Busan, Nov. 2009
  28. Shin-Kai Chen, Tay-Jyi Lin, and Chih-Wei Liu, "Parallel object detection on heterogeneous multicore platforms," in Proc. SiPS, Tampere, Oct. 2009
  29. Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, and Chih-Wei Liu, "Ultra low-power ANSI S1.11 filter bank for digital hearing aids," in Proc. ASP-DAC, Yokohama, Jan. 2009 (Special Feature Award)
  30. Tien-Wei Hsieh, Pi-Chen Hsiao, Che-Yu Liao, Hsien-Ching Hsieh, Huang-Lun Lin, Tay-Jyi Lin, Yuan-Hua Chu, and An-Yeu Wu, "Energy-effective design & implementation of an embedded VLIW DSP," in Proc. ISOCC, Busan, Nov. 2008
  31. Jwo-An Lin, Yung-Chou Tsai, Tay-Jyi Lin, and Yarsun Hsu, "Cycle stealing and channel management for on-chip networks," in Proc. HPCC, Dalian, Sep. 2008
  32. Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, and Chih-Wei Liu, "Low-power ANSI S1.11 filter bank for digital hearing aids," in Proc. ICSES, Krakow, Sep. 2008
  33. Ya-Shu Chen and Tay-Jyi Lin, "Voltage emergence prevention for energy-efficient real-time task synchronization," in Proc. CIT, Sydney, July 2008
  34. Yu-Ting Kuo, Tay-Jyi Lin, Wei-Han Chang, Yueh-Tai Li, Chih-Wei Liu, and Shuenn-Tsong Young, "Complexity-effective auditory compensation for digital hearing aids," in Proc. ISCAS, Seattle, May 2008
  35. Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, and Chih-Wei Liu, "Improving datapath utilization with composite functional units," in Proc. ISCAS, Seattle, May 2008
  36. Tay-Jyi Lin, Chun-Nan Liu, Shau-Yin Tseng, Yuan-Hua Chu, and An-Yeu Wu, "Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform," in Proc. VLSI-DAT, Hsinchu, Apr. 2008
  37. Shih-Hao Ou, Tay-Jyi Lin, Siang-Sen Deng, Chi-Hung Cho, and Chih-Wei Liu, "Multithreaded coprocessor interface for multi-core multimedia SoC," in Proc. ASP-DAC, Seoul, Jan. 2008
  38. Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Lee, Wei-Han Chang, Chih-Wei Liu, and Shuenn-Tsong Young, "Design of ANSI S1.11 filter bank for digital hearing aids," in Proc. ICECS, Marakech, Dec. 2007
  39. Hao-I Yang, Ming-Hung Chang, Tay-Jyi Lin, Shih-Hao Ou, Siang-Sen Deng, Chih-Wei Liu, and Wei Hwang, "A controllable low-power dual-port embedded SRAM for DSP processor," in Proc. MTDT, Taipei, Dec. 2007
  40. Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, and Chein-Wei Jen, "Latency-tolerant virtual cluster architecture for VLIW DSP," in Proc. ISCAS, New Orleans, May 2007
  41. Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, and Chih-Wei Liu, "Rapid C to FPGA prototyping with multithreaded emulation engine," in Proc. ISCAS, New Orleans, May 2007
  42. Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Sen Deng, and Chih-Wei Liu, "Single-issue 1500MIPS embedded DSP with ultra compact codes," in Proc. ASP-DAC, Yokohama, Jan. 2007
  43. Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, and Chein-Wei Jen, "Programmable FIR filter with adder-based computing engine," in Proc. ISCAS, Island of Kos, May 2006
  44. Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, and Chein-Wei Jen, "A 52mW 1200MIPS compact DSP for multi-core media SoC," in Proc. ASP-DAC, Yokohama, Jan. 2006 (Outstanding Design Award)
  45. Chin-Hung Liu, Tay-Jyi Lin, Chih-Wei Liu, and Chein-Wei Jen, "On-demand pipelining for improving energy-awareness," in Proc. A-SSCC, Hsinchu, Nov. 2005
  46. Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, and Chein-Wei Jen, "Architecture for area-efficient 2-D transform in H.264/AVC," in Proc. ICME, Amsterdam, July 2005
  47. Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, and Chein-Wei Jen, "Pipelining technique for energy-aware datapaths," in Proc. ISCAS, Kobe, May 2005
  48. Chia-Hsien Liu, Tay-Jyi Lin, Chih-Min Chao, Pi-Cheng Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, and Chein-Wei Jen, "Hierarchical instruction encoding for VLIW digital signal processors," in Proc. ISCAS, Kobe, May 2005
  49. Tay-Jyi Lin, Chen-Chia Lee, Chih-Wei Liu, and Chein-Wei Jen, "A novel register organization for VLIW digital signal processors," in Proc. VLSI-TSA-DAT, Hsinchu, Apr. 2005 [pdf]
  50. Shih-Hao Ou, Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, and Chein-Wei Jen, "Lightweight arithmetic units for VLSI digital signal processors," in Proc. VLSI-TSA-DAT, Hsinchu, Apr. 2005
  51. Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Cheng Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, and Chein-Wei Jen, "A unified processor architecture for RISC & VLIW DSP," in Proc. GLSVLSI, Chicago, Apr. 2005 [pdf]
  52. Chih-Chao Chen, Tay-Jyi Lin, Chih-Wei Liu, and Chein-Wei Jen, "Complexity-aware design of DA-based FIR filters," in Proc. APCCAS, Tainan, Dec. 2004
  53. Li-Chun Lin, Tay-Jyi Lin, Chen-Chia Lee, Chie-Min Chao, Shin-Kai Chen, Chia-Hsien Liu, Pi-Cheng Hsiao, Chih-Wei Liu, and Chein-Wei Jen, "A novel programmable digital signal processor for multimedia applications," in Proc. APCCAS, Tainan, Dec. 2004 (Best Paper Award)
  54. Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, and Chein-Wei Jen, "Static floating-point unit with implicit exponent tracking for embedded DSP," in Proc. ISCAS, Vancouver, May 2004
  55. Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, and Chein-Wei Jen, "A compact DSP core with static floating-point unit & its microcode generation," in Proc. GLSVLSI, Boston, Apr. 2004 [pdf]
  56. Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, and Chein-Wei Jen, "An efficient VLIW DSP architecture for baseband processing," in Proc. ICCD, San Jose, Oct. 2003 [pdf]
  57. Tay-Jyi Lin, Tsung-Hsun Yang, and Chein-Wei Jen, "Coefficient optimization for area-effective multiplier-less FIR filters," in Proc. ICME, Baltimore, July 2003 [pdf]
  58. Tay-Jyi Lin, Chin-Chi Chang, Tsung-Hsun Yang, Yu-Ming Chang, Chien-Hung Lin, Chen-Chia Lee, Hung-Yueh Lin, and Chein-Wei Jen, "Performance evaluation of ring-structure register file in multimedia applications," in Proc. ICME, Baltimore, July 2003 [pdf]
  59. Tay-Jyi Lin, Tsung-Hsun Yang, and Chein-Wei Jen, "Area-effective FIR filter design for multiplier-less implementation," in Proc. ISCAS, Bangkok, May 2003 [pdf] [ppt]
  60. Tay-Jyi Lin and Chein-Wei Jen, "CASCADE - configurable and scalable DSP environment," in Proc. ISCAS, Arizona, May 2002 [pdf]
  61. Tay-Jyi Lin and Chein-Wei Jen, "Formal equivalence checking of folded architectures," in Proc. CSCC, Crete, July 2001 [pdf] [ppt]
  62. Tay-Jyi Lin and Chein-Wei Jen, "An efficient 2-D DWT architecture via resource cycling," in Proc. ISCAS, Sydney, May 2001 [pdf] [ppt]
  63. Tay-Jyi Lin and Chein-Wei Jen, "Data stream generation for concurrent computation in VLSI signal processors," in Proc. ICSP, Beijing, Aug. 2000 [pdf]
  64. Domestic

  65. Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, and Naehyuck Chang, "Memory access aware power gating for MPSoCs," VLSI Design/CAD Symposium, Yunlin, Aug. 2011
  66. Sheng-Chieh Chuang, Yen-Ling Liu, Shu-Hsuan Chou, Shih-Chi Kuo, Keng-Jui Chang, Tay-Jyi Lin, Tien-Fu Chen, and Chi-Neng Wen, "Design and analysis of adaptive pipeline for ultra-low voltage microprocessors," VLSI Design/CAD Symposium, Kaohsiung, Aug. 2010
  67. Ming-Hsun Chuang, Yu-Ting Kuo, Kuo-Chiang Chang, Tay-Jyi Lin, and Chih-Wei Liu, "Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aids," VLSI Design/CAD Symposium, Kaohsiung, Aug. 2010
  68. Ye-Jyun Lin, Jiao-Wei Huang, Chia-Lin Yang, Tay-Jyi Lin, and Naehyuck Chang, "Hierarchical memory scheduling for multimedia MPSoCs," VLSI Design/CAD Symposium, Kaohsiung, Aug. 2010
  69. Xin-Chuan Wu, Ye-Jyun Lin, Pao-Jui Huang, Tay-Jyi Lin, and Chia-Lin Yang, "Instruction-level power estimation for embedded VLIW digital signal processors," VLSI Design/CAD Symposium, Hualien, Aug. 2009
  70. Kuo-Chiang Chang, Wei-Han Chang, Yu-Ting Kuo, Tay-Jyi Lin, and Chih-Wei Liu, "Complexity-effective dynamic range compression for digital hearing aids," VLSI Design/CAD Symposium, Hualien, Aug. 2009
  71. Jwo-An Lin, Yung-Chou Tsai, Tay-Jyi Lin, and Yarsun Hsu, "Cycle stealing buffers and physical channel management scheme for wormhole-based on-chip networks," National Computer Symposium, Taichung, Dec. 2007
  72. Shih-Hao Ou, Li-Chun Lin, Tay-Jyi Lin, Siang-Sen Deng, Ping-Hsun Wang, Yi Cho, Ching-Chih Chen, and Chih-Wei Liu, "A compact 300MHz/1500MIPS DSP with improved single-issue unit," VLSI Design/CAD Symposium, Hualien, Aug. 2006
  73. Chie-Min Chao, Tay-Jyi Lin, Chih-Wei Liu, and Chein-Wei Jen, "A simple & effective method for compiling high-level languages into application-specific processor architectures," VLSI Design/CAD Symposium, Hualien, Aug. 2005
  74. Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, and Chein-Wei Jen, "Efficient datapath design for pipelined & clustered DSP processors," VLSI Design/CAD Symposium, Hualien, Aug. 2005
  75. Shin-Kai Chen, Li-Chun Lin, Chie-Min Chao, Tay-Jyi Lin, Chih-Wei Liu, and Chein-Wei Jen, "Mapping H.264/AVC on clustered and superpipelined DSP processors," VLSI Design/CAD Symposium, Hualien, Aug. 2005
  76. Chie-Min Chao, Tay-Jyi Lin, Chen-Chia Lee, Chih-Wei Liu, and Chein-Wei Jen, "Variable-length instruction encoding for VLIW digital signal processors," VLSI Design/CAD Symposium, Kenting, Aug. 2004
  77. Shih-Hao Ou, Tay-Jyi Lin, Hung-Yueh Lin, Chih-Min Chao, Chin-Hung Liu, Chih-Wei Liu, and Chein-Wei Jen, "DSP-lite: A compact DSP core for multimedia SoC," VLSI Design/CAD Symposium, Kenting, Aug. 2004
  78. Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, and Chein-Wei Jen, "Complexity-aware coefficient quantization and effective hardware implementation of FIR filters," VLSI Design/CAD Symposium, Kenting, Aug. 2004
  79. Chie-Min Chao, Tay-Jyi Lin, Yu-Ming Chang, Hung-Yueh Lin, and Chein-Wei Jen, "Microcode generation for fixed-point DSP engines with port constraints," VLSI Design/CAD Symposium, Hualien, Aug. 2003
  80. Chien-Hung Lin, Tay-Jyi Lin, and Chein-Wei Jen, "On-demand registered pipelining for energy-aware datapath designs," VLSI Design/CAD Symposium, Hualien, Aug. 2003
  81. Tay-Jyi Lin, Tzung-Shian Yang and Chein-Wei Jen, "Coprocessing datapath generation in configurable DSP platforms," VLSI Design/CAD Symposium, Hsinchu, Aug. 2001 [ppt]

Patents

  1. Tay-Jyi Lin, Ching-Wei Yeh, Yuan-Hsiang Miao, and Shau-Chian Tang, "Video device for realtime pedaling frequency estimation," US Patent 9064153
  2. Tay-Jyi Lin, Tien-Wei Hsieh, Yuan-Hua Chu, Shih-Hao Ou, Xiang-Sheng Deng, and Chih-Wei Liu, "Multicore interface with dynamic task management capability and task loading/offloading method thereof," US Patent 8972699/ROC Patent I386814
  3. Chi-Hung Lin, Pi-Cheng Hsiao, Tay-Jyi Lin, Gin-Kou Ma, "Performance scaling device, processor having the same, and performance scaling method thereof," US Patent 8589718/ROC Patent I423017
  4. Chou-Kun Lin, Tay-Jyi Lin, Pi-Cheng Hsiao, and Yuan-Hua Chu, "Processing device for determining whether to output a first data using a first clock signal or a second data using delay from the first clock signal according to a control signal," US Patent 8499188
  5. Tay-Jyi Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen, I-Tao Liao, and Po-Han Huang, "Method and corresponding apparatus for compiling high-level languages into specific processor architectures," US Patent 7877741/ROC Patent I306215
  6. Tay-Jyi Lin, Chein-Wei Jen, Chih-Wei Liu, Po-Han Huang, Wei-Sheng Huang, and Chan-Hao Chang, "Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer," US Patent 7406588/ROC Patent I259659
  7. Tay-Jyi Lin, Pi-Chen Hsiao, Chih-Wei Liu, Chein-Wei Jen, I-Tao Liao, and Po-Han Huang, "Inter-cluster communication module using the memory access network," US Patent 7404048/ROC Patent I283411
  8. Tay-Jyi Lin, Chein-Wei Jen, Pi-Chen Hsiao, Li-Chun Lin, and Chih-Wei Liu, "Virtual cluster architecture," ROC Patent I334990
  9. Tay-Jyi Lin, Chein-Wei Jen, Chia-Hsien Liu, Chih-Wei Liu, I-Tao Liao, and Po-Han Huang, "Unified single-core processor and its program execution method," ROC Patent I318359
  10. Tse-Hao Lee, I-Tao Liao, Tay-Jyi Lin, Ming-Lun Liu, "Encoding method for very long instruction word (VLIW) DSP processor and decoding method thereof," ROC Patent I275994
  11. Chein-Wei Jen, Tay-Jyi Lin, Chin-Chi Chang, Chie-Min Chao, and Chih-Wei Liu, "Hierarchical instruction encoding for VLIW DSP and its decoding architecture," ROC Patent I266238
  12. Tay-Jyi Lin, Hung-Yueh Lin, Chein-Wei Jen, Chih-Wei Liu, and I-Tao Liao, "Static floating-point arithmetic unit for embedded digital signal processing and control method thereof," ROC Patent I258698
  13. Chein-Wei Jen, Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, and Chih-Wei Liu, "Methods for inter-cluster communication that employs register permutation," ROC Patent I227404
  14. Tay-Jyi Lin, Pao-Jui Huang, Chih-Wei Liu, Shin-Kai Chen, and Bing-Shiun Wang, "Lightweight context switch mechanism for embedded multitasking processors,"
  15. Tay-Jyi Lin, and Pi-Cheng Hsiao, "Adaptive voltage scaling system,"

Miscellaneous

  • Chao-Wei Huang, Li-Chun Lin, Shin-Kai Chen, and Tay-Jyi Lin, "A unified processor core for multimedia applications," the 1st Place Award, SIP Design Contest, Aug. 2005
  • Chen-Chia Lee, Tay-Jyi Lin, Chia-Hsien Liu, and Pi-Chen Hsiao, "A high-performance digital signal processor core," the 1st Place Award, SIP Design Contest, Aug. 2004
  • Yu-Ming Chang, Tay-Jyi Lin, Hung-Yueh Lin, and Chie-Min Chao, "A tiny DSP core for baseband processing," the 2nd Place Award, SIP Design Contest, Aug. 2003
  • Chein-Wei Jen and Tay-Jyi Lin, "Heterogeneous architecture with configurable coprocessing datapaths," International Workshop on Nanoelectronic Circuits and Giga-Microsystems (IWNCGM), Miao-Li, Oct. 2001 [ppt]
  • Tay-Jyi Lin, "A universal adapter for embedded systems," the 1st Place Award, Lattice CPLD Contest, Aug. 2000