A single-inductor two-boost dc–dc converter with bidirectional energy flow is proposed. This work combines two dc–dc converters into one by sharing a single inductor, and it is capable of storing energy and powering output load by using the bidirectional inductor current. With the storing state, the variations on the output voltage are typically negligible when the input voltage changes. According to the measured results, the converter can startup successfully with a 0.55-V input voltage. The voltage range of the storing element is 1.2–1.4 V, and the maximal output power of the proposed converter is 18 mW with its output voltage setting at 1.8 V.

This paper presents a low noise readout circuit for the optical encoder. Both absolute and incremental encoders are implemented chip with dual sensor arrays and the corresponding readout circuits. 42 columns of the pixel with adjustable dual-threshold quantizer are implemented in the absolute encoder with digitized outputs. Four quadrature sinusoidal signals dephasing 90° to each other are generated in the incremental encoder for interpolation. Two opposite phases of photodiodes placed in series are proposed for background light cancellation without adding any extra circuit. A differential transimpedance amplifier (TIA) is followed by the photodiodes to eliminate the residual signals and convert the differential currents into voltage signals. A programmable gain amplifier (PGA) is implemented to fit the input range of the following 12-b SAR ADC. Measurement results show that the SNR reaches 60dB and the maximum displacement error is 0.22μm.

This paper presents a 0.5V computational CMOS image sensor (C2IS) with array-parallel computing capability for always-on feature extraction. By applying the developed pulsed-width modulation (PWM) pixel and switch-current integration, the in-sensor 8-directional matrix-parallel multiply-accumulate (MAC) operation is realized. Moreover, the analog-domain convolution-on-readout (COR) operation, the programmable 3x3 kernel with 4-bit weights, and the tunable-resolution column-parallel ADC (1b to 8b) are implemented to achieve the real-time feature extraction without use of additional memory. The C2IS prototype has been fabricated and verified to demonstrate the raw and feature images at 480fps with a power consumption of 77/91 (uW) and the resultant FoM of 9.8/11.6 (pJ/pix/frame), respectively.

This paper presents a capacitive DC-DC converter with adaptive DC-DC conversion ratios and maximum power point tracking (MPPT) for soil and solar energy extraction. To overcome the varying input power ranges of the soil/solar energy sources, a two-dimension power tracking loop with time-based current slope detection was employed. The design was fabricated in a 0.18-μm CMOS process, achieving >80% efficiency in a throughput power range of 360μW to 25mW in the soil mode and from 400μW to 10mW in the solar mode while the peak system efficiency is 89.5%.

This paper proposes a wide f-3dB range low-pass filter (LPF) and its f-3dB calibration circuit. By using the replica LPF cell to design a oscillator and controlling the oscillation frequency, the f-3dB of LPF could be programmable among different process corners. Simulation results show that the calibrated f-3dB frequency has an error about 6% to the target frequency. The power consumption of the calibration system is about 3.7% to the LPF core.

In this paper, we present a high precision bandgap voltage reference (BGR) circuit with calibration technique to reduce process variation. In traditional BGR circuits, the process variation can be calibrated to achieve near-zero voltage variation by first order compensation, but the temperature coefficient is still varying from 5 to 50 ppm/˚C in different processes corner. In order to get more precise reference voltage, a new compensation circuit is implemented in this paper to accomplish second order compensation. The proposed circuit can automatically calibrate the reference voltage of BGR circuit when BJTs and MOSFETs are operated in TT corner and Resistors operate in any process corner. The BGR circuit is realized in TSMC 0.18-μm CMOS process occupying active area of 0.8217 mm2. The average temperature coefficient is 29.39 ppm/˚C at temperature from 0˚C to 120 ˚C, the average power consumption is 104.94 μW under 1.8-V supply voltage, and power supply rejection ratio (PSRR) are –39.6 dB@100 Hz and -40.7 dB@1 kHz.

Electrostatic discharge (ESD) protection design is needed for integrated circuits; however, the ESD protection devices beside the I/O pad may cause negative impact on the circuit performance. To achieve both excellent ESD robustness and good broadband performance, a silicon-controlled rectifier (SCR) with trigger diodes and matching inductor to form a novel distributed diode-triggered SCR (π-SCR) is presented in this work. As compared with the conventional π-diode in silicon, the π-SCR can reduce the clamping voltage during the critical positive-to-VSS (PS) ESD test, and the high-frequency performance is not seriously degraded (insertion loss < 2dB within 0-20GHz in this work). Besides, the π-SCR does not suffer the latchup issue in low-voltage CMOS technology, and it has the potential to further reduce the clamping voltage during other ESD tests. Therefore, the π-SCR will be a good choice for broadband ESD protection in CMOS technology.