(A)  Journal Publication

  1. Z.Z. Wu, S.C. Chang, ¨Synthesis for Multiple Input Wire Replacement of a Gate: Theorems and Applications〃 accepted to IEICE Transaction.
  2. S.C. Chang, D. I. Cheng, C.W. Yeh, ¨Dealing with Multiple Redundancies in Combinational Circuits〃 accepted to IEE Computers and Digital Techniques.
  3. C.H. Cheng, T.K. Tien, Y.C. Shen, and S.C. Chang, ¨Functional Slack Time Computation of Logic Gate〃 accepted to JSIEE.
  4.  S.C. Chang, Z. Z. Wu, "Theorems and Extensions of Single Wire Replacement," accepted to IEEE Transaction on Computer Aided Design.
  5. S. C. Chang, C,H. Cheng, W.B. Jone, S.D. Li and J.S. Wang, "Charge Sharing Alleviation and Detection for CMOS Domino Circuits," IEEE Transaction on Computer Aided Design, Vol 20, pp. 266-280, 2001.
  6. W. B. Jone, D. C. Huang, S. C. Chang and S. R. Das, ¨Defect Level Estimation for Pseudorandom TestingUsing Stochastic Analysis,〃 VLSI Design: An International Journal of Custom-Chip Design, simulation, and Testing.
  7. S. C. Chang, K. Y. Chen, W.B. Jone and S. R. Das "Random pattern testability enhancement by circuit rewiring" accepted to VLSI Design: An International Journal of Custom Chip Design, Simulation, and Testing.
  8. S.C. Chang, and J.C. Rau, "A Timing Driven Pseudo Exhaustive Testing for VLSI circuits,"  IEEE Transaction on Computer Aided Design, Vol. 20, pp. 147-157, Jan. 2001.
  9. C.H. Cheng, W.B. Jone, S. C. Chang, and J. S. Wang,¨Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits,〃 IEE Electronics Letters, Vol. 36, No. 20, pp. 1684-1685, Sep. 2000.
  10. J. C. Rau, W. B. Jone, S. C. Chang, and Y. L. Wu, "A Tree-Structured LFSR Synthesis Scheme for Pseudo-Exhaustive Testing of VLSI Circuits," IEE Proceedings - Computers and Digital Techniques, Vol.147 - (5), pp. 343-348, Sep. 2000.
  11. S.C. Chang, K.J. Lee, Z.Z. Wu, and W.B.Jone, "Reducing Test Application Time by Scan Flip-Flop Sharing," IEE proceeding-Computes and Digital Techniques, Vol. 147, pp. 42-52, Jan., 2000
  12. S.C. Chang, W.B. Jone and S.S. Chang, ¨TAIR: Testability Analysis by Implication Reasoning,〃IEEE Transaction on Computer Aided Design, Vol. 19, pp. 152-160, 2000.
  13. S.C. Chang, L.V.Ginneken, and M. Marek-Sadowska, "Circuit Optimizations by Rewiring," IEEE Transaction on Computer, Vol. 48, pp. 962-970, 1999.
  14. S. C. Chang and I. H. Cheng, ¨Efficient Boolean Division and Substitution Using Reduxndancy Addition and Removal,〃IEEE Transaction on Computer Aided Design, Vol. 18, pp. 1096-1106, 1999.
  15. S.C. Chang, K.T. Cheng, N.S. Woo, and M. Marek-Sadowska, "Post Layout Logic Restructuring Using Alternative Wires," IEEE Transaction on Computer Aided Design, Vol. 16, pp. 587-596, 1997.
  16. S.C. Chang, M. Marek-Sadowska, and K.T. Cheng,"Perturb and Simplify: Multi-level Boolean Network Optimizer," IEEE Transaction on Computer Aided Design, Vol. 15, pp. 1494-1504, Nov., 1996.
  17. S.C. Chang, M. Marek-Sadowska and T.T. Hwang, "Technology mapping for TLU Type FPGA based on decomposition of Binary Decision Diagram," IEEE Transaction on Computer Aided Design, pp. 1126-1236, Oct., 1996.

(B)  Conference Publication

1.     J. H. Jiang, W. B. Jone, and S. C. Chang,¨Embedded Core Testing Using Broadcast Test Architecture,〃 accepted to DFT2001.

2.     Y.H. Su, C. H. Cheng, S.C. Chang, and C.W. Yeh, "Novel Techniques for Improving Testability Analysis, " Proc. IEEE the Ninth Asian Test Symposium, ATS, PP. 392-397, 2000.

3.     C. H. Cheng, J.S. Wang, S.C. Chang, and W.B. Jone, "Charge Sharing Fault Analysis and Testing for CMOS Domino Logic," Proc. IEEE the Ninth Asian Test Symposium, ATS, PP. 435-440, 2000.

4.     C. H. Chen, S. C. Chang, S. T. Le, W. B. Jone, and J.S. Wang, "Synthesis of CMOS Domino Circuits for Charge Sharing alleviation," Proc. IEEE/ACM,  International Conference on Computer Aided Design, ICCAD, pp. 387-340, 2000.

5.     S. C. Chang, Z. Z. Wu, and H. J. Yu, "Wire Reconnection Based on Implication Flow Graph," Proc. IEEE/ACM,  International Conference on Computer Aided Design, ICCAD, pp. 533-537, 2000.

6.     C. H. Cheng, J. S. Wang, S. C. Chang, and W. B. Jone, "Scan-Resistant Charge-Sharing Fault in Domino Circuit," IEEE Computer Society Annual Workshop on VLSI.

7.     C. H. Cheng, J. S. Wang, S. C. Chang, and W. B. Jone, "Charge Sharing Fault Analysis and Testing for CMOS Domino Logic," 1st IEEE Latin-American Test Workshop, pp. 59-64, 2000.

8.      J.C.Rau, Y.M.Chen, and S.C. Chang, "A Compact Factored Form for a Boolean   Function," Proc. of IEEE International symposium on Circuits And Systems, vol. II, pp. 317-320, 2000.

9.     S.C. Chang, and J.C.Rau, "A Timing-Driven Pseudo-Exhaustive Testing of VLSI Circuits," Proc. of IEEE International Symposium on Circuits And Systems, vol. II, pp. 665-668, 2000.

10.  S.C. Chang, J.C. Chuang, and Z.Z. Wu, ¨Multiple Input Wire Replacement for Wiring Consideration,〃 Proc. IEEE/ACM,  International Conference on Computer Aided Design, ICCAD, pp. 115-118, 1999.

11.  C.H. Cheng, S.C. Chang, J.S. Wang, and W.B. Jone, "Charge Sharing Fault Detection for CMOS Domino Logic Circuits," Proc. The 10th VLSI/CAD symposium, pp. 175-178, 1999.

12.  S.C. Chang, K. J. Lee, Z. Z. Wu, and W. B. Jone, "Test Application Time Reduction by Input Signal Sharing,〃Proc. The 10th VLSI/CAD symposium, pp. 115-118, 1999.

13.  C.W. Yeh, M.C. Chang, S.C. Chang, and W.B. Jone, ¨Power Reduction Through Iterative Gate Sizing and Voltage Scaling〃 IEEE International Symposium on circuits and Systems, ISCAS Vol I, pp. 246-249, 1999.

14.  C. H. Cheng, S. C. Chang, J. S. Wang and W. B. Jone, ¨Charge Sharing Fault Detection for CMOS Domino Logic Circuits,〃 Proc. International Symposium on Defect & Fault Tolerance in VLSI System, pp. 77-85, 1999.

15.  C.W. Yeh, M.C. Chang, S.C. Chang, and W.B. Jone, ¨Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications,〃 Proc. Design Automation Conference DAC, pp. 68-71, 1999.

16.  S.C. Chang, K.Y. Chen, W.B. Jone, and S.R. Das, ¨Random Pattern Testability Enhancement by Circuit Rewiring," Proc. IEEE  International conference on VLSI design, pp. T9.4, 1999.

17.  S.C. Chang, S.S. Chang, W. B. Jone, and C.C. Tsai, ¨An Efficient Technique for Enhancing Combinational Testability Measurement,〃Proc. The 9th VLSI Design/CAD Symposium, pp. 145-148, 1998.

18.  S.C. Chang, S.S. Chang, W.B. Jone, and C.C Tsai, ¨A Novel Combinational Testability Analysis by Considering Signal Correlation," Proc. IEEE  International Test Conference, ITC, pp. 658-667, 1998.

19.  W.B. Jone, J.C. Rau, S.C. Chang, and Y.L. Wu, "A Tree-Structured LFSR Synthesis Scheme for Pseudo-Exhaustive Testing of VLSI Circuits," Proc. IEEE  International Test Conference,  ITC, pp. 22-330, 1998.

20.  S. C. Chang, and I. Cheng, " Efficient Boolean Division and Substitution ," Proc. IEEE/ACM Pro. Design Automation Conference DAC, pp. 342-347, 1998.

21.  S.C. Chang, I. Cheng, C.W. Yeh, "On Removing Multiple Redundancies in Combinational Circuits," Proc. IEEE/ACM Design, Automation and Test in Europe, DATE, pp. 738-742, Feb., 1998.

22.  C.W. Yeh, M.C. Chang, S.C. Chang, W.B. Jone, and J.S. Wang, "Reducing Power Consumption by Iterative Gate Sizing and Voltage Scaling," Proc. The 8th VLSI Design/CAD Symposium, , pp.281-283, 1997.

23.  S.C. Chang, L.Van Ginneken, and M. Marek-Sadowska, "Fast Boolean Optimization by Rewiring," Proc. IEEE/ACM,  International Conference on Computer Aided Design, ICCAD, pp. 262-269, 1996.

24.  S.C. Chang, M. Marek-Sadowska, "Perturb and Simplify: Optimizing Circuits with External Don't Cares", Proc. IEEE/ACM,  Europe Design Automation Conference, EDAC, pp. 8a-1, 1996.

25.  S.C. Chang, K-T Cheng and M. Marek-Sadowska, "An efficient algorithm for local don't cares calculation," Proc. IEEE/ACM Pro. Design Automation Conference, DAC,  pp. 663-667, 1995.

26.  C-C Lin, K.C. Chen, S.C. Chang, and M. Marek-Sadowska, "Logic Synthesis for engineering Change", Proc. IEEE/ACM Pro. Design Automation Conference, DAC, pp. 647-652, 1995.

27.  S.C. Chang and M. Marek-Sadowska,  "Perturb and Simplify: Multi-level Boolean network Optimizer," Proc. IEEE/ACM  International Conference on Computer Aided Design, ICCAD,  pp. 2-5, 1994.

28.  S.C. Chang, K-T Cheng, Nam-Sung Woo and M. Marek-Sadowska,  "Layout Driven Logic Synthesis for FPGA," Proc. IEEE/ACM Pro. Design Automation Conference, DAC, pp. 308-313.

29.  S.C. Chang, David Ihsin Cheng, and M. Marek-Sadowska, "Minimizing ROBDD size of Incompletely Specified functions", Proc. IEEE/ACM,  Europe Design Automation Conference, EDAC, pp 620-624,1994.

30.  D.I. Cheng, S.C. Chang and M. Marek-Sadowska, "Partitioning Combinational Circuits in Graph and Logic Domains", Proc. SASIMI, pp 404-412, 1993.

31.  S.C. Chang and M. Marek-Sadowska, "BDD Representation of Incompletely Specified Functions", International Workshop on Logic Synthesis, 1993.

32.  S.C. Chang and M. Marek-Sadowska, "Technology Mapping and Circuit Depth Optimization for Field Programmable Gate Array", Proc. CICC, pp. 3.5.1-3.5.4, 1993.

33.  S.C. Chang and M. Marek-Sadowska, "Technology Mapping via Transformation of Function Graphs", Proc. IEEE/ACM  International Conference on Computer Design, ICCD, pp.159-162, 1992.