Verifiable Embedded Real-Time Application Framework

Pao-Ann Hsiung Feng-Shi Su, Chuen-Hau Gao, Shu-Yu Cheng, and Yu-Ming Chang
Department of Computer Science and Information Engineering
National Chung Cheng University, Chiayi-621, Taiwan.
(In Proceedings of the IEEE International Real-Time Technology and Applications Symposium (RTAS'01),
Work-In-Progress Session, (Taipei, Taiwan), pp. 109-110, IEEE Computer Society Press, May 2001.)


A new application framework called Verifiable Embedded Real-Time Application Framework (VERTAF) is proposed for embedded real-time application development, with the aim of reducing design errors and increasing design productivity. VERTAF is an integration of three technologies: object-oriented, software component, and formal verification. It consists of five software components: Implanter, Modeler, Scheduler, Verifier, and Generator. Experiences of using VERTAF show a significant increase in design productivity through design reuse, and a significant decrease in design time and effort through design verification.

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