#ifndef CPUDATAWIDTH
  #define CPUDATAWIDTH 64	//64-bit
#endif
////SFR
#define	sfr_debugport	S0
#define	sfr_intrctrl	S1 //b0=ENA,b1=ENARET,b2=mode,b3=moderet
#define	sfr_intren	S2 //Interrupt Enable, b0~b7 for trap 0x10~0x17
#define	sfr_intrpriority S3	 //Interrupt Priority,1=high,0=low,b0~7 for trap 0x10~0x17
#define	sfr_IRA		S4 //Interrupt return address
#define	sfr_PBANK	S5 //Predict bank, 0~15
#define	sfr_PRED	S6 //Predict flag set 0
#define	sfr_ioctrl	S7 //b0=icacheinvalid,b1=dcacheinvalid,b2=T0star,b3=T1start
#define	sfr_TC0		S8 //Reload counter of timer T0
#define	sfr_TC1		S9 //Reload counter of timer T1
#define	sfr_T0		S10 //Increase every clock, Interrupt 0x10 when T0=TC0 then rewind to 0
#define	sfr_T1		S11 //Increase every clock, Interrupt 0x11 when T1=TC1, then rewind to 0

//Bit of intrctrl
#define	b_INTR_ENA	0x01	//b0=0:disable interrupt, @reset=0
#define	b_INTR_ENARET	0x02	//b1=ENA at reti; @interrupt:{b1,b0}={b0,0}; @reti:b0=b1
#define	b_INTR_MODE	0x04	//b2:0=os mode;1=user mode; @reset=0
#define	b_INTR_MODERET	0x08	//b3=MODE at reti; @interrupt:{b3,b2}={b2,0}; @reti:b2=b3

//Bit of ioctrl
#define b_T0_start	0x01	//start T0 upcounter
#define b_T1_start	0x02	//start T1 upcounter
#define	b_T0_overflow	0x04	//T0 is counted
#define	b_T1_overflow	0x08	//T0 is counted
#define b_icacheinvalid	0x10	//b4=1:invalid icache
#define b_dcacheinvalid	0x20	//b5=1:invalid dcache
#define b_icacheinvalidbusy	0x40	//b6=1:icache is invaliding, always 0
#define b_dcacheinvalidbusy	0x80	//b7=1:dcache is invaliding, need wait 2 nop


#define ret	jmp.reg R31
#define	stop	HALT
#define	STI	WriteSFR.or	sfr_intrctrl,b_INTR_ENA
#define	StartT0	WriteSFR.or	sfr_ioctrl,b_T0_start
#define	StartT1	WriteSFR.or	sfr_ioctrl,b_T1_start
#define	StopT0	WriteSFR.and	sfr_ioctrl,~b_T0_start
#define	StopT1	WriteSFR.and	sfr_ioctrl,~b_T1_start

//Port for SystemC simulation only
#define	a_Key	0x40FFFFF8
