International Journal of Embedded Systems
Special Issue on
Hardware-Software Codesign for Systems-on-Chip

Notification Extended: January 31, 2004

Call for Papers HTML || PDF || Text

With the rapidly permeating global trend of adopting SoC (System-on-Chip) design technologies, traditional hardware-software codesign techniques need adaptation and revamping to satisfy the growing needs of complex system designs. This special issue is devoted to presenting state-of-the-art SoC codesign and coverification methodologies, languages, techniques, tools, system architectures, and related technologies. Prospective papers should be unpublished and present solid research work offering innovative contributions either from a methodological or application point of view.


Topics of interest include (but are not limited to):

Design & Verification Methodologies Soft/Hard IP-reuse in Codesign
Design & Verification Languages Embedded Software Issues
Design & Verification Tools Embedded Hardware Issues
SoC Architectural Issues Communication Issues
SoC Physical Impact on Codesign Cosimulation Techniques
Nanotechnology and Codesign (Semi)-Formal Verification
Mixed-Signal in Codesign Platform-Based Codesign Issues

Paper Format

The format of the paper should be as detailed in the following URL: Basically, it is IEEE Transactions style, either in Word or Latex2E, not exceeding 6000 words (which is no more than 15 pages of the journal).

Paper Submission

Submit papers to the guest editor by sending your manuscript in PDF format as an attachment to an e-mail. Guest Editor E-mail:

Important Dates

Manuscript due: December 15, 2003 (Extended and Hard!!!)
Acceptance notification: January 31, 2004
Final manuscript due: February 6, 2004
Publication date: June 2004

Guest Editor

Pao-Ann Hsiung
Department of Computer Science and Information Engineering
National Chung Cheng University
Chiayi, Taiwan-621, R.O.C.

Editorial Board

Last Updated: 2 December, 2003