SoC Design Flow and Tools
The purpose of these labs is to make you familiar with the computer-aided
design and verification tools for Electronic System-Level (ESL) design.
All labs are to be completed within TWO (2) weeks after it is assigned.
Late submissions will be graded as follows: (Original Points) * (0.8)^(No. of days late)
LIST OF LABS:
- Cadence SystemC/Verilog/VHDL simulators
- UML Editor and Simulator
- Mentor Seamless Co-Verification Environment (CVE)
- FPGA design tools
- Altera Quartus II v3.0, SoPC Builder
- Xilinx ISE Foundation, and other tools
- Coware ConvergenSC
- Tensilica Xtensa Configurable Processor
- All slides and notes downloadable from this page are to be used only for
this course, by the students taking this course, and by the professor.
Any other use of any sort requires explicit permission from the slide author.
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