Invited Talk

Special Topics in Computer Science
Department of Computer Science and Information Engineering
National Chung Cheng University
April 7, 2003

Bus Delay Reduction for Deep Submicron Technology



While the technology parameters get into deep sub-micron, interconnection wire delay influences a chip performance greater than gate delay. Especially, bus is consumed by interconnect delay. Many techniques for interconnect delay reduction based on buffer insertion have been presented. In general, the propagation delay signal ran on interconnections is considered on RC model and exhibits tolerance error as compared to SPICE. The inductance effect in RC model is almost neglected since the work frequency is not high enough. However, the frequency of current chips has worked over 1GHz, the inductance existed in interconnection cannot be neglected again and it is becoming more important with faster on-chip rise times and longer wire length. Thus, the calculation of propagation delay has transferred to the consideration of RLC model for high performance chip. Fewer papers investigated on RLC mode have contributed to the interconnection delay estimation.

We propose an algorithm to reduce the propagation delay in a multi-source multi-sink bus with considering RLC model for the bus. The algorithm based on buffer or repeater insertion and sizing is employed to minimize the maximum delay in a bus. Experimentally, the results for some test examples are the delay reduction of 48%, 87.42%, and 62.63% in average for 0.18 .m, 0.35.m and 0.5.m technologies, respectively.