COSYMA (COSYnthesis for eMbedded micro Architectures) is a platform for exploration of the co-synthesis process. Beginning with rather small target architectures and single input programs it has developed into a design system for fairly complex time constrained multi process systems and larger heterogeneous target architectures. So far, the system has mainly been used for design-space exploration where it gives fast response times which are not available in a purely manual design process.
How to get Cosyma
The tools for mapping a specification in terms of a Quenya CDFG onto a co-processor based target architecture are currently available in the LYCOS tutorial.
... ... Large heterogeneous systems are often composed of several components, such as microprocessors, dedicated hardware, external devices, and memories, interconnected by general or local buses, using a variety of communication protocols. Selecting the best combination of components is a prerequisite for ending up with the best result of the subsequent phases of the design process which include functional partitioning and hardware/software/communication synthesis
Peter V. Knudsen and Jan Madsen Communication Estimation for Hardware/Software Codesign 6th International Workshop on Hardware/Software Codesign, Codes/CASHE'98
Jan Madsen and Bjarne Hald An Approach To Interface Synthesis 8th International Symposium System Synthesis, 1995
Lycos on-line publications(most of the papers are not available)
Polis (almost everything is available on-line)
The purpose of this project is to solve some problems met in industry. The problems they want to solve can be found in the preface of their book (pp. 11~12 of the PostScript file), Hardware-Software Co-Design of Embedded Systems: The Polis Approach.
Due to the problems they want to solve, this project is more concentrated on the formal specification, formal verification and co-simulation. Unlike most of the other tools (cosyma, cosmos, etc.), they put almost no attention on the system level partitioning and scheduling. They leave the decisions of partitioning and scheduling to the designers, and provide the designers with an environment to quickly evaluate their decisions through formal verification or system co-simulation. They also put more effort on software synthesis and estimation than the other tools.
Chinook (the tool is not available on-line)
Chinook is a hardware-software co-synthesis CAD tool for embedded systems. It is designed for control dominated, reactive systems under timing constraints, with a new emphasis on distributed architectures. Current topics include synthesis of run-time support, communication synthesis, and efficient and accurate co-simulation.
Akka (Manual available, tool not available on-line, but might be available by email)
The input to the system is an executable functional description written in C or C++. The C/C++ description is compiled three times to: capture the design structures, generate an executable for execution profiling and generate an executable for data transfer profiling.The two executables are executed, and the captured profiling data is written to a data base as shown in figure 1. The description is also analyzed with a hardware estimator which writes the estimation result to the same database as the profilers. Analysis results in the data base are fed to a hardware/software partitioning algorithm, and to a graph browsing tool which allows the user to guide the partitioner. When the user or tool have selected a hardware and software partition, it is written to the database. This information is read by the GNU C compiler which generates the VHDL code for the objects selected for hardware, and replaces the object in the C/C++ description with interfaces to hardware. Generated hardware and software can be co-simulated before and after synthesis, behavioural and RT-level co-simulation. AKKA also supplies a prototyping environment based on a Sparc workstation and a hardware emulation board called the EVC1.
Their On-line Publications
CASTLE/SIR(Both source and binaries are available)
CASTLE supports the flow of the codesign of hardware and software and the rapid prototyping of embedded systems. A large variety of tools is available including component models, hardware/software partitioning aids and synthesis paths starting with a given specification in C, C++, VHDL, or Verilog.
CASTLE stands for Codesign And Synthesis Tool Environment. SIR is the database format within CASTLE. SIR stands for System Intermediate Representation. SIR/CASTLE was meant to be a toolkit, which you should be able to adapt to your own requirements. In the SYDIS project at GMD, it is used as the base for doing hardware/software codesign. Your interest may be in simulation or synthesis, for instance.
CodeSign(Version 1.1 available on-line)
A little introduction paper (2 pages PostScript)
The project is driven by the need for method and tools to design complex real-time embedded systems ... ... . The project intends to develop a codesign methodology and associated tools. The main research topics of CODE SIGN can be described as:
M. Eisenring and J. Teich. Domain-Specific Interface Generation From Dataflow Specifications. Proc. of Codes/CASHE'98, the 6th Int. Workshop on Hardware/Software Codesign, Seattle, Washington (U.S.A.), pages 43-47, March 1998.
Other Papers by Dr. Jürgen Teich (Project leader of CodeSign)
CoWare and Symphony (It is a commercial tool now!)
This was a project in Design Technology Division of IMEC. It is closely related to DSP and Telecommunication.
... ... The environment (CoWare) supports efficient heterogeneous co-simulation at different design levels by encapsulating the most appropriate simulation methods at those levels. The environment also builds upon existing synthesis and compilation techniques by encapsulating them and supports system design flows by providing design methodology management support ... ...
... ... Symphony provides integrated support for hardware/software communication, real-time kernel support for the coordination of software tasks, and system integration and interface synthesis support for correctly integrating different hardware and software components together into application-specific architectures ... ...
Bill Lin, Steven Vercauteren, `` Synthesis of Concurrent System Interface Modules with Automatic Protocol Conversion Generation '', IEEE International Conference on Computer-Aided Design, November 1994.
The Complete List of Publications of the Project.
The Ode System (tool not available on-line)
Ode System is a toolset aimed on the Hardware-/Software-Codesign of distributed systems. The hardware and software components are derived from a single SDL-specification. The system is divided into three components: Partitioning, Software generation, Hardware generation. The partition tool exploits the implicit parallelism of the specified system. It generates software and hardware files. The specification parts dedicated to hardware are then transformed into a VHDL description. This permits the use of a broad range of target FPGA-architectures. The processes determined to be implemented in software are compiled into ANSI-C.
COOL (tool is not available on-line)
COOL is a hardware/software codesign tool which has been developed for dataflow dominated systems. COOL uses a subset of VHDL for specification. A graphical user interface has been developed to specify these systems in a structural and hierarchical way. These systems are stored in a system library. In addition, the graphical user interface is used to define target architectures and design constraints. The target architectures are organized in a target architecture library too. The main objective of COOL is heterogeneous implementation. Several algorithms for hardware/software partitioning have been developed allowing the designer
Tools Use Ptolemy Extensions in HW/SW codesign(tools are not available)
1) PeaCE (National Soul University of Korea)
PeaCE is the codesign environment for rapid development of heterogeneous digital systems. Ptolemy in the acronym is the design tool developed at the Univ. of California at Berkeley, on which we're building the improved environment for hardware-software codesign. For concurrent and interactive design, we need to provide the following capabilities: unified hardware/software representation, hardware/software partitioning, heterogeneous simulation at different levels of abstraction, and hardware/software synthesis. Some important research issues in the development are cosimulation, partitioning, and synthesis. Also, as a test vehicle for our environment, we design a prototyping board that consists of a DSP and a FPGA.
2) Design Assist (Asawaree Kalavade, Ph.D thesis at UC Berkeley)
The abstract and table of content of the thesis: SYSTEM-LEVEL CODESIGN OF MIXED HARDWARE-SOFTWARE SYSTEMS
Asawaree Kalavade's On-line Publications, Patents, and Talks
SynDEx (Available on-line)
SynDEx is a system level CAD software, supporting the "Algorithm Architecture Adequation" (AAA) methodology, for rapid prototyping and optimizing the implementation of real-time embedded applications on multicomponent architectures.
This is a tool focussed on real-time systems. It is not for circuit synthesis. The architecture of the system has to be provided by the user. For each chosen architecture SynDEx proposes the best implementation of the algorithm application onto this architecture. Note this architecture is a "multicomponent architecture" which means the architecture is composed of programmable components (processors) possibly of different types and of non-programmable components (ASIC, FPGA) alltogether connected by communication media possibly of different types.
Some other projects and tools
Other Relative Papers:
Generation of Interconnect Topologies for Communication Synthesis [p 36] M. Gasteier, M. Münch, and M. Glesner, DATE 98.
Ti-Yen Yen and Wayne Wolf, "Communication synthesis for distributed embedded systems," in Proceedings, ICCAD-95, IEEE Computer Society Press, 1995, pp. 288-294
Papers by Ti-Yen Yen on Real Time Distributed Embedded systems
Hardware-Software Co-Synthesis of Fault-Tolerant Real-Time Distributed Embedded Systems Niraj K. Jha, Santhanam Srinivasan, Euro-DAC' 95
Interface Logic Generation for VHDL-Specified Components, Jeff Collins, Smita Bakshi, and Karl Nelson, submitted to the CODES/CASHE '98 conference
C. A. Valderrama, François Naçabal, Pierre Paulin, A. A. Jerraya, Automatic generation of interfaces for distributed c-vhdl cosimulation of embedded systems: an industrial ex perience (96) 7th International Workshop on Rapid Systems Prototyping, June 1996, Greece. Suported by a Brazilian Governement Fellowship CAPES/COFECUB 144-94 Brazil.
J.M.Daveau, T.Ben Ismail, and A.A.Jerraya, "Synthesis of System Level Communication by an Allocation Based Approach"", Proceedings ISSS, September 1995. (pp.150~155 of the 8th ISSS proceedings, available at room 353, we looked at this paper very briefly before)
Papers by people in COSMOS project
A.Basu, R.S.Mitra and P. Marwedel, "Interface Synthesis for Embedded Applications in Codesign Environment", Proc. 11th International Conference on VLSI Design, Chennai, India, 1998. postscript
Other's Group/People's Link to HW/SW Codesign and Related Links
1) Dr. Walker's links to CAD and Codesign
2) Hiroyuki TOMIYAMA's CAD Links (Kyushu University, Japan)
3) Klaus Buchenrieder's Bibliography of Hardware/Software Codesign and Links to other Sources on Hardware/Software Codesign
4) Design Methodology Research (Akka)'s Links to Related Sites
5) Gupta's Links to HW/SW Co-design Pages
6) Chinook's Links to Embeded Sytems Pages
7) Dr. Philip Koopman's page for Embedded Communications.