What's New?

• Fall 2001 Term Projects
• Project Details will be announced soon

Deadlines

Details

• Proposals should include:
  • Project title,
  • Member list (Indicate the SPEAKER),
  • 100-200 words abstract in English.
• Presentations should include:
  • 10-15 slides,
  • 15-20 minutes presentation,
  • 5-10 minutes Q/A (by teacher and by other groups),
  • bonus points will be given to good questions and to good answers.
• Reports should be submitted as follows:
  • Submit at least the following 3 electronic files using e-mail:
    1. A written report in MS-Word or LaTeX format (see below for details),
    2. An input file used for verifying your model (such as *.s, etc.), and
    3. A "README.TXT" file containing details on how you executed your verification model such as commands used, etc.)
  • Written report should consist of:
    • 1 cover page with project title, member list (mark speaker name), and workload distribution.
    • At least 10 pages of contents in the following order:
      • Abstract (100 to 200 words),
      • Introduction (background on your topic, motivation, etc.),
      • System Model (all timed automata) and Specification Property for verification,
      • Verification Procedure (your method, difficulties overcomed, how, etc.)
      • Verification Results (tool output, property verified or not, etc.)
      • Conclusion(lessons learned, etc.)

Rules

• A team may consist of one or more students.
• Only one project need be accomplished by one team.
• The role of each team member must be made explicit before project begins.
• Items to be handed in at the end of project:
  1. System Design Results (experiment data, software programs, etc.)
  2. Project Report (at least 10 pages)
  3. A Project Presentation is required!
• Project Grading (total = 15%):
  • Results Presentation: 10%
  • Written Report: 5%

Project Topics (choose one!)

• Verify a communication protocol (Bluetooth, 802.11, ATM, WAP, etc.)
  • Protocol modeled by extended timed automata (ETA)
  • Protocol requirements specified in CTL
  • Verification results
• Verify a piece of real-time embedded software (RTES)
  • Software and hardware modeled by ETA
  • RTES requirements specified in CTL
  • Verification results
• Verify a System-on-a-Chip (SoC)
  • SoC modeled by ETA
  • SoC design requirements specified in CTL
  • Verification results
• Develop & Implement your own state-space reduction technique (BONUS: 40%)
  • Algorithm for your reduction technique
  • Proof of correctness for your algorithm
  • Implementation of your algorithm in SGM
  • Application examples
  • Reduction results
• Develop a counterexample graphical viewer (signal timing diagram, MSC, UML sequence diagram, ...) (BONUS: 40%)
  • Representation modeling (how is a counterexample represented by your selected view from above)
  • Proof of equivalence (counterexample == represented view)
  • Implementation in SGM
  • Application examples
• Develop an interface in SGM for Safecharts (BONUS: 50%)
  • Input syntax for Safecharts
  • Semantics storing for Safecharts
  • Translation from Safecharts to extended timed automata
• Develop an interface in SGM for UML State Machines (formerly called Statecharts) (BONUS: 40%)
  • Input syntax for State Machines
  • Semantics storing for State Machines
  • Translation from State Machines to extended timed automata

Project Groups and Presentation Schedule (to be updated)

Project Report Schedule

Notice

• All projects and notes downloadable from this page are to be used only for this course, by the students taking this course, and by the professor. Any other use of any sort requires explicit permission from the author. Click here to request permission.

Last Updated: February 19, 2006.