Publication
List of Prof.
Jiun-In Guo
【Journal
Papers】
| [1] |
J. I. Guo,
C. M. Liu, and C. W. Jen, "The Efficient Memory-Based VLSI Array
Designs for DFT and DCT", IEEE Transactions on Circuits and
Systems, vol.39, no.10, pp.723-733, Oct. 1992.
|
| [2] |
J.
I. Guo,
C. M. Liu, and C. W. Jen, "A New Array Architecture for Prime Length
Discrete Cosine Transform", IEEE Transactions on Signal
Processing, vol.41, no.1, pp.436-442, Jan. 1993.
|
| [3] |
J.
I. Guo,
Chingson Chen, and C. W. Jen, "Unified architecture for discrete
cosine transform, sine transform and their inverses", Electronics
Letters, 12th October, vol.31, no.21, pp.1811-1812, 1995.
|
| [4] |
J.
I. Guo,
C. M. Liu, and C. W. Jen, "A Novel CORDIC-Based Array Architecture
for the Multi-Dimensional Discrete Hartley Transform,"IEEE
Transactions on Circuits and Systems II, vol.42, no.5,
pp.349-355, May. 1995.
|
| [5] |
Jui-Cheng Yen, J. I. Guo,
and Hun-Chen Chen,”A New k-Winners-Take-All Neural Network
and Its Array Architecture”, IEEE Transactions on Neural Network,
vol. 9, no 5, pp.901-912, September 1998.
|
| [6] |
J. I. Guo,”A
memory-based approach to design efficient VLSI arrays for the
multi-dimensional discrete Hartley transfom", Proceedings of the
National Science Council, ROC, Part A, vol. 23, no.2,
pp.289-302, 1999.
|
| [7] |
J. I. Guo,”An
Efficient Parallel Adder Based Design for One Dimentional Discrete
Fourier Transform", Proceedings of the National Science Council,
ROC, Part A, vol.24, no.3, pp.195-204, May 2000.
|
| [8] |
Jui-Cheng Yen and J. I. Guo,
“A New Hierarchical Chaotic Image Encryption Algorithm and its VLSI
Realization”, IEE Proceedings, Vision, Image and Signal
Processing, vol. 147, no. 2, pp. 167-175, April 2000.
|
| [9] |
Jui-Cheng Yen and J. I. Guo,
“A New Chaotic Mirror-Like Image Encryption Algorithm and its VLSI
Architecture”, Pattern Recognition and Image Analysis, vol.10, no.2, pp.236-247, 2000.
|
| [10] |
J.
I. Guo,
“A New Distributed Arithmetic Algorithm and its Hardware
Architecture for the Discrete Hartley Transform”, Pattern
Recognition and Image Analysis, vol.10, no.3, pp.368-378, 2000.
|
| [11] |
J. I. Guo,
“An Efficient Design for One Dimensional Discrete Hartley Transform
Using Parallel Additions”, IEEE Transactions on Signal Processing,
vol. 48, no. 10, pp.2806~2813, Oct. 2000.
|
| [12] |
J.
I. Guo, "An Efficient Parallel Adder Based Design for One Dimensional
Discrete Cosine Transform", IEE Proceedings Circuits,
Devices, and Systems, vol.147, no. 5, pp.276-282, Oct. 2000.
|
| [13] |
T. S. Chang, J. I. Guo,
and C. W. Jen,”Hardware Efficient DFT Designs with Cyclic
Convolution and Subexpression Sharing”, IEEE Transactions on
Circuits and Systems II, vol. 47, no. 9, pp. 886-892, Sep. 2000.
|
| [14] |
H. C. Chen, J. I. Guo,
and Y. C. Tzeng, “Characterizations of Gate Delay in Cell Library
using Dynamic Learning Neural Network”, Journal of National
Lien-Ho Institute of Technology, vol. 17, pp.105-114, 2000.
|
| [15] |
J. I. Guo
and C. C. Li, “A Generalized Architecture for the One Dimensional
Discrete Cosine and Sine Transforms”, IEEE Transactions on
Circuits and Systems for Video Technology, vol. 11, no. 7, pp.
874-881, July. 2001.
|
| [16] |
Jui-Cheng Yen and J. I. Guo , “The Design and Realization of a Chaotic Neural Signal Security System”, Pattern Recognition and Image Analysis,
vol.12, no.1, pp.70-79, 2002.
|
| [17] |
J. I. Guo,
Jui-Cheng Yen, and H. F. Pai, ”A New Voice Over Internet Protocol
Technique with Hierarchical Data Security Protection”, IEE
Proceedings- Visions, Images, and Signal Processing, vol. 149,
no. 4, pp. 237-243, August 2002.
|
| [18] |
J. I. Guo,“A
New Hardware Efficient Design Approach for the 1-D Discrete Fourier
Transform”, Pattern Recognition and Image Analysis, vol.12,
no.3, pp. 299-307, 2002.
|
| [19] |
J.
I. Guo,
Chih-Ta Chien, and Chien-Chang Lin, “A Low Power Parameterized
Hardware Design for the One Dimensional Discrete FOURIER Transform
of Variable Lengths”,
Journal of Circuits, Systems, and
Computers,
vol. 11, no. 4, pp.405-426, 2002.
|
| [20] |
J. I. Guo
and Jui-Cheng Yen, “An Efficient IDCT Processor Design for HDTV
Applications” Journal of VLSI Signal Processing, vol. 33,
pp. 147-155, 2003.
|
| [21] |
Jui-Cheng Yen and J. I. Guo,
“The Design and Realization of a new Domino Signal Security System”, accepted as a full paper by the Journal of The Chinese Institute
of the Electrical Engineering,
vol. 10, no. 1, pp. 69~76, 2003.
|
| [22] |
Hun-Chen
Chen, J. I. Guo, Lin-Chieh Huang, and Jui-Cheng Yen,”Design
and Realization of a New Signal Security System for Multimedia Data
Transmission”, EURASIP Journal on Applied Signal
Processing, 2003:13, pp. 1291-1305.
|
| [23] |
J. I. Guo,
Rei-Chin Ju, and Jia-Wei Chen, “An Efficient 2-D DCT/IDCT Core
Design using Cyclic Convolution and Adder-based Realization”,
IEEE Transactions on Circuits and Systems for Video Technology,
vol. 14, no. 4,
pp. 416~428,
April. 2004.
|
| [24] | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh and Jia-Wei Chen, “A Power-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms”, accepted by IEEE Transactions on Circuits and Systems for Video Technology, Special Issue on Integrated Multimedia Platforms, May. 2004.
|
| [25] | Chih-Da Chien, Chien-Chang Lin, Chung-Hang Yang, and Jiun-In Guo , “Design and Realization of a New Hardware Efficient IP Core for the 1-D Discrete Fourier Transform”, accepted by IEE Proceedings Circuits, Devices, and Systems ,May. 2004 . |
| [26] | Hun-Chen Chen, Jiun-In Guo , Chein-Wei Jen, and T. S. Chang, “A New Distributed Arithmetic Realization of Cyclic Convolution and Its DFT Application”, accepted by IEEE Proceedings Circuits, Devices, and Systems ,May. 2004.
|
| [27] | Hun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo , and Chein-Wei Jen, “ The Long Length DHT Design with A New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning”, accepted by IEICE Transactions on Electronics, Dec. 2004.
|
| [28] | Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, and Chein-Wei Jen, “A Memory Efficient Realization of Cyclic Convolution and its Application to Discrete Cosine Transform” ,accepted by IEEE Transactions on Circuits and Systems for Video Technology, Nov. 2004.
|
【
Conference Papers
| [1] |
J.
I. Guo, C. M. Liu, and C. W. Jen, "New systolic arrays for
prime length discrete cosine transform," Proc. IEEE Workshop
on Visual Signal Processing and
Communications, Hsinchu, Taiwan,
R.O.C., pp.67-70, June, 1991.
|
| [2] |
J.
I. Guo, C. M. Liu, and C. W. Jen, "A memory-based approach
to design and implement systolic arrays for DFT and DCT,"
Proc. 1992 IEEE International Conference on Acoustics, Speech,
and Signal Processing, vol.5, pp. V-621~V-624, 1992.
|
| [3] |
J.
I. Guo, C. M. Liu, and C. W. Jen,"A two-level pipelined
systolic array chip for computing the discrete cosine
transform," Proc. 1993 International Symposium on VLSI
Technology, Systems, and Applications, May 12-14, pp.199-203,
1993.
|
| [4] |
J.
I. Guo, C. M. Liu, and C. W. Jen,"A memory-based systolic
array chip for the 1-D discrete cosine transform," Proc. 1993
Fourth VLSI DESIGN/CAD Workshop, pp.96-100, Aug. 26-28,
1993.
|
| [5] |
J.
I. Guo, C. M. Liu, and C. W. Jen, "A CORDIC-based VLSI array
for computing 2-D discrete Hartley transform," Proc. 1993
IEEE International Symposium on Circuits and Systems, May
3-6, pp.1571-1574, 1993.
|
| [6] |
Y. S.
Lin, J. I. Guo, and C. W. Jen, "A multi-phase shared bus
structure for fast Fourier transform," Proc. 1993 IEEE
International Symposium on Circuits and Systems, May 3-6,
pp.1575-1578, 1993.
|
| [7] |
J.
I. Guo, C. M. Liu, and C. W. Jen,"A novel VLSI array design
for the discrete Hartley transform using cyclic convolution,"
Proc. 1994 IEEE International Conference on Acoustics, Speech,
and Signal Processing, April 19-22, 1994.
|
| [8] |
J.
I. Guo, C. M. Liu, and C. W. Jen,"A general memory-based
approach to design efficient VLSI arrays for the
multi-dimensional discrete Hartley transform," Proc.1994 IEEE
International Symposium on Circuits and Systems, May 30 -
June 2, 1994.
|
| [9] |
J.
I. Guo,
C. M. Liu, and C. W. Jen, "A VLSI Array Design for Discrete
Fourier Transform Using Distributed Arithmetic," Proc. 1995
ROC Tenth Technical Education Conference, pp.359-368, May
1995.
|
| [10] |
J. I. Guo and C. W. Jen,"A systolic algorithm and architecture for the
fast cosine transform," Proc. National Computer Symposium
1995 Republic of China, vol.1, pp.98-105, Dec. 1995.
|
| [11] |
J.
I. Guo and Jason Wang "A Programmable Memory-Based Data Sequencer for
Video Signal Processing," Proc. 1997 ROC 20th Technical
Education Conference, pp.109-118, April 1997.
|
| [12] |
Jui-Cheng
Yen and J. I. Guo,”A New Hierarchical Chaotic Image
Encryption Algorithm and Its Hardware Architecture,” Proc.
1998 Ninth VLSI DESIGN/CAD Symposium, Aug. 19-22, 1998.
|
| [13] |
Jui-Cheng
Yen and J. I. Guo,”A New Chaotic Image Encryption
Algorithm,” Proc. 1998 National Symposium on
Telecommunications, pp.358-362, Dec. 18-19, 1998.
|
| [14] |
J.
I. Guo,”The
Design of Memory-based VLSI Array for One-Dimensional Discrete
Hartley Transform,” Proc. 1998 National Symposium on
Telecommunications, pp.63-68, Dec. 18-19, 1998.
|
| [15] |
T. S. Chang, J. I. Guo,
and C. W. Jen,”
A
Compact IDCT Processor for HDTV Applications,”
Proc. 1999 IEEE Workshop on SiGNAL PROCESSING
SYSTEMS (SiPS) Design and implementation,
pp.151-158, Oct. 20-22, Taipei, Taiwan, R.O.C.
|
| [16] |
Jui-Cheng
Yen and J. I. Guo,”A
New Image Encryption Algorithm and Its VLSI Architecture,”
Proc. 1999 IEEE Workshop on SIGNAL PROCESSING SYSTEMS (SiPS)
Design and implementation, pp.430-437, Oct. 20-22, Taipei,
Taiwan, R.O.C.
|
| [17] |
J.
I. Guo,”An
Efficient Parallel Adder Based Design for the One Dimensional
Discrete Hartley Transform,” Proc. 1999 Tenth VLSI DESIGN/CAD
Symposium, pp.247-250, Aug. 18-21, 1999.
|
| [18] |
J.
I. Guo
and Jui-Cheng Yen,”A New Mirror-Like Image
Encryption Algorithm and Its VLSI Architecture,” Proc. 1999
Tenth VLSI DESIGN/CAD Symposium, pp.327-330, Aug. 18-21,
1999.
|
| [19] |
Jui-Cheng
Yen and J. I. Guo,”A Chaotic Neural Network for Signal
Encryption/Decryption and Its VLSI Architecture,” Proc. 1999
Tenth VLSI DESIGN/CAD Symposium, pp.319-322, Aug. 18-21,
1999.
|
| [20] |
Hun-Chen Chen, Jiun-In Guo and Chein-Wei Jen,” LOW POWER
MODULE DESIGNS FOR VIDEO CODEC SYSTEMS,” Proc. 1999 Tenth
VLSI DESIGN/CAD Symposium, pp.275-278, Aug. 18-21, 1999.
|
| [21] |
Jiun-In
Guo, Jui-Cheng Yen, and Jen-Chieh Yeh, “The design and
realization of a new hierarchical Chaotic image encryption
algorithm”, Proc. 1999 International Symposium on
Communications, pp. 210-214, Nov. 7-10, 1999.
|
| [22] |
Jui-Cheng
Yen and J. I. Guo,”A new MPEG/encryption system and its
VLSI architecture,” Proc. 1999 International Symposium on
Communications, pp.215-219, Nov. 7-10, 1999.
|
| [23] |
Jui-Cheng
Yen and J. I. Guo,”A New Neural MPEG/Encryption System,”
Proc. 1999 WORKSHOP on Consumer Electronics: Digital Video and
Multimedia Communications, pp.119-122, Oct. 18-19, Taipei,
Taiwan, R.O.C.
|
| [24] |
J.
I. Guo,”An
Efficient Design for One Dimensional Discrete Cosine Transform
Using Parallel Adders,” Proc. 2000 IEEE International
Symposium on Circuits and Systems, pp.V-725~V.728, May
28-31, GENEVA, SWITZERLAND, 2000.
|
| [25] |
Jui-Cheng
Yen and J. I. Guo,”A New Chaotic Key-Based Design for
Image Encryption and Decryption,” Proc. 2000 IEEE
International Symposium on Circuits and Systems,pp.IV-49~IV-52,
May 28-31, GENEVA, SWITZERLAND, 2000.
|
| [26] |
J.
I. Guo,
J. C. Yen, and S. F. Pai, “An Internet Telephony System Design
with Hierarchical Data Security Protection,” Proc. 2000
WORKSHOP on Consumer Electronics: Digital Video, 3C and
Information Appliance, pp. 56-61, Oct.19-20, Taipei, Taiwan,
R.O.C.
|
| [27] |
C. C.
Li, and J. I. Guo, “A General Design for the One
Dimensional Discrete Cosine and Sine Transforms,” Proc. 2000
National Symposium on Telecommunications, pp.1-320~1-325,
Dec. 15-16, Chun-Li, Taiwan, R.O.C.
|
| [28] |
J.
I. Guo,
“A Low Cost 2-D Inverse Discrete Cosine Transform design for
Image Compression,” Proc. 2001 IEEE International Symposium
on Circuits and Systems, pp.IV-658~IV-661, May 6-9, Sydney,
Australia, 2001.
|
| [29] |
J.
I. Guo, “A New DA-Based Array for
One Dimensional Discrete Hartley Transform,“ Proc. 2001 IEEE
International Symposium on Circuits and Systems,
pp.IV-662~IV-665, May 6-9, Sydney, Australia, 2001.
|
| [30] |
J. I. Guo,
Jia-Wei Chen, and Cheng-Chung Wu, “An Efficient Adder-Based 2-D
DCT/IDCT Design for Image Compression Applications,” Proc.
2001 20th VLSI DESIGN/CAD Symposium, Aug. 15-17, 2001.
|
| [31] |
J. I. Guo, Jui-Cheng
Yen, and Jo-Yo Lin, “The FPGA Realization of a New Image
Encryption/Decryption Design,” Proc. 2001 Twelveth VLSI
DESIGN/CAD Symposium, Aug. 15-17, 2001.
|
| [32] |
Jui-Cheng Yen and J. I. Guo,” Design of a
New Signal Security System,”Proc. 2002 IEEE
International Symposium on Circuits and Systems,
pp. IV-121~IV-124,
May
26-May 29, Scottsdale, Arizona, U.S.A, 2002.
|
| [33] |
H. C. Chen, J. I. Guo, and C. W. Jen, “A
New Group Distributed Arithmetic Design for the One Dimensional
Discrete Fourier Transform,” Proc. 2002 IEEE
International Symposium on Circuits and Systems,,
pp. I-421~I-424
May
26-May 29, Scottsdale, Arizona, U.S.A, 2002.
|
| [34] |
J.
I. Guo
and
Chien-Chang Lin,
“A
New Hardware Efficient Design for the One Dimensional Discrete
Fourier Transform”,
Proc.2002 IEEE International Symposium on Circuits and Systems,
pp. V-549~V-552,
May
26-May 29, Scottsdale, Arizona, U.S.A, 2002.
|
| [35] |
Chien-Chang Lin,
Chih-Da Chien,
and J. I. Guo, “A Parameterized Hardware Design
for the Variable Length Discrete Fourier Transform,”
Proc. 2002 VLSI DESIGN/CAD Symposium, Aug. 12-15, 2002,
Taiwan, R.O.C.
|
| [36] |
Rei-Chin Ju,
Li-Tin Yeh, and
J. I. Guo, “A Low Power Parameterized Hardware Core Design
for the Discrete Cosine and Sine Transforms,” Proc. 2002 VLSI
DESIGN/CAD Symposium, Aug. 12-15, 2002, Taiwan, R.O.C.
|
| [37] |
H. C.
Chen, and J. I. Guo, “A New Group Distributed Arithmetic
Approach and Hardware Design for One Dimensional Discrete
Hartley Transform,” Proc. 2002 VLSI DESIGN/CAD Symposium,
Aug. 12-15, 2002, Taiwan, R.O.C.
|
| [38] |
Hun-Chen Chen, Jui-Cheng Yen, and J. I. Guo,
“
Design of a New Cryptography
System,” Proc. The Third IEEE Pacific-Rim Conference
on Multimedia 2002 (PCM2002), Dec. 16~18, Taiwan, R.O.C.
|
| [39] |
J. I. Guo,
Chien-Chang Lin, and Chih-Da Chien,”
A Low Power Parameterized Hardware Design for the One
Dimensional Discrete FOURIER Transform,”
Proc.
2002
IEEE International Symposium on Intelligent Signal Processing
and Communication Systems (ISPACS 2002), pp. 407-411, Nov.
21~24, Taiwan, R.O.C.
|
| [40] |
J. I. Guo,
Chiun-Chau Lin, Min-Chih Tsai, and Sheng-Wei Lin,”
An Efficient Voice over Internet Protocol Technique Combining
the Speech Data Encryption and G.729 Error Recovery,”
Proc.
2002
International Computer Symposium (ICS2002),
Dec. 18~21, Taiwan, R.O.C.
|
| [41] |
J. I. Guo,
Jia-Wei Chen, and Han-Chen Chen, “A New 2-D 8x8 DCT/IDCT Core
Design using Group Distributed Arithmetic,” Proc. 2003 IEEE
International Symposium on Circuits and Systems, May 25-May
28, Bangkok, Thailand, 2003.
|
| [42] |
J. I. Guo,
Chih-Da Chien, and, Chien-Chang Lin,
”
A Parameterized Low Power Design for the Variable-Length
Discrete FOURIER Transform using Dynamic Pipelining,” Proc.
2003 IEEE International Symposium on Circuits and Systems,
May 25-May 28, Bangkok, Thailand, 2003.
|
| [43] | Hun-Chen Chen, J. I. Guo, and Chien-Wei Jen, “A Memory Efficient Realization of Cyclic Convolution and its Application to Discrete Cosine Transform,” Proc. 2003 IEEE International Symposium on Circuits and Systems, May 25-May 28, Bangkok, Thailand, 2003.
|
| [44] |
W.
C. Lee, C. H. Yang, C. M. Liu and J. I. Guo, “Perceptual
Convolution for Reverberation”, Proc. of 115th AES
Convention, Oct. 10-13, Jacob K. Javits Convention Center,
New York, USA, 2003.
|
| [45] |
W. C. Lee,
C. M. Liu, C. H. Yang, and J. I. Guo, “Fast Perceptual
Convolution for the Room Reverberation”, Proc. of the 6th
International Conference on Digital Audio Effects (DAFX-03),
Queen Mary, University of London, September 8-11, 2003.
|
| [46] |
Hun-Chen Chen, Lin-Chieh Huang,
Jui-Cheng Yen, and J. I. Guo, “DESIGN AND IMPLEMENTATION
OF A NEW CHAOTIC SIGNAL SECURITY SYSTEM FOR MULTIMEDIA
APPLICATIONS,” Proc. 2003 VLSI DESIGN/CAD Symposium,
Aug. 12-15, Taiwan, R.O.C, 2003.
|
| [47] |
Kuan-Hung
Chen, Jiun-In Guo, Jinn-Shyan Wang Ching-Wei Yeh, and
Tien-Fu Chen,
“A POWER-AWARE IP CORE DESIGN FOR
THE VARIABLE-LENGTH DCT/IDCT AT MPEG4 SHAPE-ADAPTIVE TRANSFORMS,”
Proc. 2004 IEEE International Symposium on
Circuits and Systems,
May 23-May 26, Vancouver, Canada, 2004.
|
| [48] |
Rei-Chin Ju, Jia-Wei Chen,
Jiun-In Guo, and Tien-Fu Chen, “A PARAMETERIZED POWER-AWARE
IP CORE GENERATOR FOR THE 2-D 8x8 DCT/IDCT, “ Proc. 2004 IEEE
International Symposium on Circuits and Systems, May 23-May
26, Vancouver, Canada, 2004.
|
| [49] |
Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo,
and Tien-Fu Chen,
“A POWER-AWARE IP CORE GENERATOR FOR THE ONE-DIMENSIONAL DISCRETE FOURIER TRANSFORM,”
Proc. 2004 IEEE International Symposium on
Circuits and Systems,
May 23-May 26, Vancouver, Canada, 2004.
|
| [50] |
Chih-Da Chien,
Chien-Chang Lin, and Jiun-In Guo,“A
PARAMETERIZED IP CORE GENERATOR FOR THE ONE-DIMENSIONAL
LONG-LENGTH DISCRETE FOURIER TRANSFORM,” Proc. 2004 IEEE
International Symposium on Nanoelectronic Circuits and Gigascale
Systems (ISNCGS2004), Feb. 12-13, Miao-Li, Taiwan, 2004.
|
| [51] |
Kuan-Hung Chen, Jiun-In Guo,
Jinn-Shyan Wang, and Ching-Wei Yeh, “A DCT/IDCT IP Core Design
for Multimedia Transform Coding,“ Proc. 2004 IEEE
International Symposium on Nanoelectronic Circuits and Gigascale
Systems (ISNCGS2004), Feb. 12-13, Miao-Li, Taiwan, 2004.
|
| [52] |
Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien,
Chien-Chang Lin, and Jiun-In Guo, “A HIGH-PERFORMANCE
BITSTREAM PROCESSING IP CORE DESIGN FOR MPEG4 VIDEO COMPRESSION
APPLICATIONS,“ Proc. 2004 IEEE
International Symposium on Nanoelectronic Circuits and Gigascale
Systems (ISNCGS2004), Feb. 12-13,
Miao-Li, Taiwan, 2004.
|
| [53] | Hun-Chen Chen, Jui-Cheng Yen, Jiun-In Guo and Chi-Shiung Lin, Design and Implementation of a K-Winners-Take-All Neural Network,” Proc.2004 IEEE International Symposium on Nanoelectronic Circuits and Gigascale Systems (ISNCGS2004), Feb. 12-13, Miao-Li, Taiwan, 2004.
|
| [54] |
Tai-Lun
Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, and Jiun-In
Guo,“A HIGH-PERFORMANCE MPEG4 BITSTREAM PROCESSING CORE,” Proc. 2004 IEEE International Conference on Multimedia & Expo,
June 27-30, Taipei, Taiwan, 2004.
|
| [55] | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, and Ching-Wei Yeh,“A Power-Aware SNR-Progressive DCT/IDCT IP Core Design for Multimedia Transform Coding,”Proc. 2004 IEEE International Conference on Multimedia & Expo, June 27-30, Taipei, Taiwan, 2004.
|
| [56] |
Chien-Chang Lin, Hsiu-Cheng Chang, Kuan-Hung Chen, and Jiun-In Guo ,“Reconfigurable Low Power MPEG-4 Texture Decoder IP Design,”Proc. 2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004) , Tainan, Taiwan, December 6-9, 2004 .
|
| [57] |
Tai-Lun Chang, Ying-Ming Tsai, Hsiu-Cheng Chang, Chih-Da Chien, and Jiun-In Guo ,” A High-Performance Reconfigurable Multi-MPEG Bitstream Processing IP Core,” Proc. 2004 VLSI DESIGN/CAD Symposium , Aug. 10-13, Taiwan, R.O.C, 2004.
|
| [58] | Hsiu-Cheng Chang, Chien-Chang Lin, Ming-Chih Tsai, Kuan-Hung Chen, and Jiun-In Guo , “ Parameterized Multi-MPEG Texture Decoder IP Design,” Proc.2004 VLSI DESIGN/CAD Symposium , Aug. 10-13, Taiwan, R.O.C, 2004 .
|
| [59] | Hsiu-Cheng Chang, Chien-Chang Lin, and Jiun-In Guo, “A Novel Low-Cost High-Performance VLSI Architecture for MEPG AVC/H.264 CAVLC Decoding,” Proc. 2005 IEEE International Symposium on Circuits and Systems , May 23-May 26, Kobe, Japan, 2005.
|
| [60] | Kuan-Hung Chen, Jiun-In Guo, and Jinn-Shyan Wang, “High-Performance Direct 2-D Transform Coding IP Design for MPEG-4 AVC/H.264,” Proc. 2005 IEEE International Symposium on Circuits and Systems, May 23-May 26, Kobe, Japan, 2005.
|
| [61] | Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, and Jiun-In Guo, “A Low-Power Motion Compensation IP Core Design for MPEG-1/2/4 Video Decoding,” Proc. 2005 IEEE International Symposium on Circuits and Systems , May 23-May 26, Kobe, Japan, 2005.
|
| [62] |
Kuan-Hung Chen, Jiun-In Guo, Kuo-Chuan Chao, Jinn-Shyan Wang, and Yuan-Sun Chu, “High-Performance Low power Direct 2-D Transform Coding IP Design for MPEG-4 AVC/H.264 with switching power suppression technique,” Proc. 2005 IEEE VLSI-TSA, International Symposium on VLSI Design, Automation & Test (VLSI-DAT), April 27-29, Hsinchu, Taiwan, R.O.C. 2005.
|
Last Updated: Jan 06,
2005