Ching-Che Chung (鍾菁哲)
Assistant
Professor
Department of
Computer Science and Information Engineering
EA415,
工學院一館 EA415 (中正大學地圖
CCU MAP)
電話(TEL): (05) 272-0411 分機(EXT): 33129
E-mail: wildwolf_AT_cs.ccu.edu.tw
學經歷
(Professional Background):
[2008.08 - Present] 國立中正大學 資訊工程學系 助理教授
[2008.1 – 2008.08] 國立交通大學 晶片系統研究中心 博士後研究
[2004.1 – 2008.01] 國立交通大學 電子研究所系統組 博士後研究
[1998.9 – 2003.09] 國立交通大學 電子研究所系統組 博士
1.
Wireless
and Wireline Communication Systems
2.
Low-Power
and System-on-a-Chip (SOC) Design Technology
3.
Mixed-Signal
IC Design
4.
All-digital
Phase-Locked Loop/Delay-Locked Loop and Its Applications
矽感測器與系統實驗室
(Silicon Sensor and System
Lab, S3Lab):
開設課程
(Open Courses):
1.
工程數學(Engineering Mathematics)
2.
數位積體電路設計 (Design of Digital Integrated Circuits
and Systems)
已發表著作
(期刊 Journal Papers):
1.
Jui-Yuan Yu, Ching-Che
Chung, and Chen-Yi Lee, “A Symbol-Rate Timing Synchronization Method for
Low Power Wireless OFDM Systems”, in IEEE
Transactions on Circuits and Systems II: Express Briefs, Vol. 55, pp. 922-926,
Sep. 2008 [pdf] [SCI
, EI]
2. Duo Sheng,
Ching-Che Chung, and Chen-Yi Lee, “An
Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications“, in IEEE
Transactions on Circuits and Systems II: Express Briefs, Vol. 54, pp.
954-958, Nov. 2007. [pdf] [SCI , EI]
3. Pao-Lung Chen, Ching-Che Chung, Jyh-Neng
Yang, and Chen-Yi Lee, “A clock generator with cascaded dynamic frequency counting
loops for wide multiplication range applications,” in IEEE Journal of Solid-State Circuits, Vol. 41, pp. 1275-1285, Jun.
2006. [pdf] [SCI , EI]
4. Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee, “A Portable
Digitally Controlled Oscillator Using Novel Varactors,
“ in IEEE
Transaction on Circuits and System II: Analog and Digital Signal Processing,
Vol. 52, pp. 233-237, May 2005. [pdf] [SCI , EI]
5. Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee, “A Novel
Digitally-Controlled Varator for Portable Delay Cell
Design, “ in IEICE
Tran. Fundamentals, Vol. E87-A, pp. 3324-3326, Dec. 2004. [pdf] [SCI , EI]
6. Ching-Che Chung and Chen-Yi Lee, “A new
DLL-based approach for all-digital multi-phase clock generation,” in IEEE Journal of Solid-State Circuits,
Vol. 39, pp. 469-475, Mar. 2004. [pdf] [SCI , EI]
7. Ching-Che Chung and Chen-Yi Lee, “An
all-digital phase-locked loop for high-speed clock generation,” in IEEE Journal of Solid-State Circuits,
Vol.38, pp. 347-351, Feb. 2003. [pdf] [SCI , EI]
已發表著作
(國際會議 Conference Papers):
1. Jui-Yuan Yu, Ching-Che
Chung, Wan-Chun Liao and Chen-Yi Lee, “A sub-mW
Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network
Applications,” in Digest of Technical Papers, IEEE
Solid-State Circuits Conference, pp. 364-365, Feb. 2007. [pdf] [EI]
2.
Jui-Yuan Yu, Juinn-Ting
Chen, Mei-Hui Yang, Ching-Che
Chung, and Chen-Yi Lee, “An all-digital phase-frequency tunable clock
generator for wireless OFDM communications systems,” in Proceeding of 2007 IEEE International SOC Conference, pp. 305-308,
Sep. 2007. [EI]
3. Duo Sheng,
Ching-Che Chung, and Chen-Yi Lee, “A
Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications,” in
Proceedings of 2006 IEEE Asia Pacific Conference on Circuits and Systems,
pp. 105-108, Dec. 2006.
4. Tsu-Ming Liu, Ching-Che
Chung, Ting-An Lin, Sheng-Zen Wang, and Chen-Yi
Lee, “Design of a 125uW, Fully-Scalable MPEG-2 and H.264/AVC Video Decoder for
Mobile Applications,” in Proceedings of
43rd Design Automation Conference, pp. 288-289, Jul. 2006. [pdf] [EI]
5. Jui-Yuan Yu, Ching-Che
Chung, Hsuan-Yu Liu, Yu-Wei Lin, Wan-Chun Liao, Terng-Yin Hsu, and Chen-Yi Lee, “A 31.2mW UWB Baseband
Transceiver with All-Digital I/Q-mismatch Calibration and Dynamic Sampling,” in
Digest of Technical Papers, Symposium on
VLSI Circuits,
Circuit Sessions 26, Jun. 2006. [EI]
6. Duo Sheng,
Ching-Che Chung, and Chen-Yi Lee, “An
All-Digital Phase-Locked Loop with High Resolution For SoC
Applications,” in Proceedings of
International Symposium on VLSI Design, Automation, and Test, pp. 207-210,
Apr. 2006. [EI]
7. Ching-Che Chung, Pao-Lung
Chen, and Chen-Yi Lee, “An All-Digital Delay-Locked Loop for DDR SDRAM
Controller Applications,” in Proceedings
of International Symposium on VLSI Design, Automation, and Test, pp.
199-202, Apr. 2006 [EI]
8. Pao-Lung Chen, Ching-Che Chung and Chen-Yi Lee, “An
all-digital PLL with cascaded dynamic phase average loop for wide
multiplication range applications,” in
Proceedings of IEEE International Symposium on Circuits and Systems, pp.
4875-4878, May 2005. [EI]
9. Hsuan-Yu Liu, Chien-Ching
Lin, Yu-Wei Lin, Ching-Che Chung,
Kai-Li Lin, Wei-Che Chang, Lin-Hung Chen, Hsie-Chia Chang, and Chen-Yi Lee, “A 480Mb/s
LDPC-COFDM-based UWB baseband transceiver, “ in Digest of Technical Papers, IEEE Solid-State Circuits Conference,
pp. 444-446, Feb. 2005. [pdf] [EI]
10. Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Ching Lin, Ching-Che Chung, Terng-Yi
Hsu, and Chen-Yi Lee, “A COFDM baseband processor with robust synchronization
for high-speed WLAN applications, “ in Digest
of Technical Papers, Symposium on VLSI Circuits, pp. 156-159, Jun. 2004. [EI]
11. Hsie-Chia Chang, Ching-Che
Chung, Chien-Ching Lin, and Chen-Yi Lee, “A
300MHz Reed-Solomon decoder chip using inversionless
decomposed architecture for Euclidean algorithm,” in Proceedings of 28th European
Solid-State Circuits Conf. (ESSCIRC), pp. 519-522, Sep. 2002.
12. Ching-Che Chung and Chen-Yi Lee, “An
all-digital phase-locked loop for high-speed clock generation,” in Proceedings of IEEE International Symposium
on Circuits and Systems, Vol. 3, pp.26-29, May 2002. [EI]
13. Ching-Che Chung and Chen-Yi Lee, “A Novel
Structure for Portable Digitally Controlled Oscillator,” in Proceedings of IEEE International Symposium
on Circuits and Systems, Vol. 1, pp.272-275, May 2001. [EI]
14. Yew-San Lee, Ching-Che Chung, Tsyr-Shiou
Perng, Li-Chyun Hsu,
Ming-Yang Jaw, and Chen-Yi Lee, “A memory-based architecture for very high
throughput variable length codec design,” in Proceedings of IEEE International Symposium on Circuits and Systems,
pp. 9-12, June 1997. [EI]
已發表著作
(Ph.D. Dissertation):
博士論文：
應用於系統晶片設計之自動化合成時序鎖相迴路
Automatic
Synthesis of Timing-Locked Loops for SoC Designs [pdf]
專利(Patents):
1. Ching-Che Chung, and Chen-Yi Lee,”Digital Loop Filter for Low-Jitter All-Digital
Phase-Locked Loop Design,” US/TW/JPA patent, Filed on Jul. 2008.
演講記錄(Speeches):
1.
”All-Digital
PLL/DLL Design and Its Applicationss”, 國立交通大學電信系,
2.
”Low-Power SoC
Design”, 國立成功大學電機系,
3. “Low-Power SoC
Physical Design”, 國立中正大學資工系,