Current Research Areas:(visit CAD at UCSB )

• Logic optimization using ATPG techniques:
• S. C. Chang, Ihsin Cheng, " Efficient Boolean Division and Substitution ," Proc. DAC pp. 342-351, 1998.
• S.C. Chang, M. Marek-Sadowska, and K.T. Cheng, "Perturb and Simplify: Multi-level Boolean Network Optimizer", IEEE Transaction on Computer Aided Design, Vol. 15, pp. 1494-1504, Nov, 1996.
• S.C. Chang, L. VanGinneken and M. Marek-Sadowska Fast Boolean Optimization by Rewiring , ICCAD pp. 262-269 ,1996 .
• S.C. Chang, I. Cheng, C.W. Yeh, "On Removing Multiple Redundancies in Combinational Circuits," Proc. IEEE/ACM Design, Automation and Test in Europe, pp. 738-742, Feb, 1998.
• Design for testability, BIST
•  S.C. Chang, S.S. Chang, W.B. Jone, C.C Tsai, "A Novel Combinational Testabiilty Analysis by Considering Signal Correlation," IEEE Pro. International Test Conference (ITC), pp.  658-667, 1998.
• W.B. JOne, J.C. Rau, S.C. Chang, and Y.L. Wu, "A Tree-Structured LFSR Synthesis Scheme for Pseudo-Exhaustive Testing of VLSI Circuits," IEEE Pro. International Test Conference (ITC), pp. 322-330, 1998.
• BDD synthesis and its applications
• S.C. Chang, David Ihsin Cheng, and M. Marek-Sadowska, Minimizing ROBDD size of Incompletely Specified functions , Proc. EDAC pp 620-624. 1994.
• FPGA related optimization
• S.C. Chang, M. Marek-Sadowska and T.T. Hwang, Technology Mapping for TLU Type FPGA based on Decomposition of Binary Decision DiagramIEEE Transaction on Computer Aided Design, Vol. 15, pp.1126-1236, Oct, 1996.
• S.C. Chang, K.T. Cheng, N.S. Woo, M. Marek-Sadowska, " Post Layout Logic Restructuring Using Alternative Wires ", IEEETransaction on Computer Aided Design,Vol. 16, pp.587-596, June, 1997.
• S.C. Chang, K-T Cheng, Nam-Sung Woo and M. Marek-Sadowska, Layout Driven Logic Synthesis for FPGA ,Proc. DAC, pp. 308-313 1994.
• Circuit partitioning and Engineering change
• D. Cheng, S.C. Chang and M. Marek-Sadowska, Partitioning Combinational Circuits in Graph and Logic Domains , Proc. SASIMI, pp 404-412. 1993.
• C.C. Lin, K.C. Chen, S.C. Chang, M. Marek-Sadowska and K.T. Cheng Logic Synthesis for Engineering Change Proc. DAC, pp. 647-652, 1995.